zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
1,001 Commits
1 Branch
0 Tags
23 MiB
Commit Graph

3 Commits (1613f7fb4148c3bf10ec8d99c69da56b60df7d35)

Author SHA1 Message Date
Istvan Csomortani aa7b0bb4dd VC707 basesys: General fixes, actual status: working 
- Add an auxiliary cpu interconnect
	- Add an auxiliary interrupt concatenation module
	- Add new MIG file, current frequency of the DDR interface is 100
	  Mhz
	- Memory interconnect optimisation strategy is 'Maximize
	  Performance'
 2014-03-24 13:07:48 +02:00
Istvan Csomortani 75963ab376 Initial check in of VC707 base project 
- All source files for the VC707 base project
	- Update the common base system to the new naming convention
 2014-03-10 17:26:17 +02:00
Rejeesh Kutty ddac1a8834 added common board files 2014-02-28 21:17:01 -05:00