Adrian Costina
f566268db5
zed_common: Updated common to 2014.4
2015-01-08 11:59:26 +02:00
Istvan Csomortani
7ae003cf82
zed_base: Interrupt update
2014-10-30 19:00:05 +02:00
Istvan Csomortani
10b898a62d
zed_base: Fix IRQ layout.
...
Just a temporally fix of IRQ layout.
2014-10-27 14:46:26 +02:00
Istvan Csomortani
5deffd57b1
zed: Remove top level constraints
...
Remove top level constraints from the ZED base design.
2014-10-20 13:20:27 +03:00
Lars-Peter Clausen
7d3be14ab5
common: Connect audio clkgen reset
...
While we are at it also hide the unused locked pin.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:44:46 +03:00
Lars-Peter Clausen
fd89458708
common: Set cpu interconnect strategy to minimize area
...
There will rarely be concurrent access to the peripheral control bus
interconnect, so there is no need to optimize for performace. Setting the
interconnect strategy to minimize area can reduce the resource usage by
~90%.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:43:54 +03:00
Lars-Peter Clausen
43e9b0c7a6
common: Disable TTC0 MMIO routing for PS7
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We do not use the ttc0 to MMIO routing, but it is enabled by default, so
explicitly disable it.
2014-10-10 16:19:51 +03:00
Adrian Costina
041d8faaf7
common: Updated common projects for ac701/kc702/zc702/zed to vivado 2014.2
2014-09-30 10:31:00 +03:00
Lars-Peter Clausen
41cc92ef49
Remove BASEADDR/HIGHADDR parameters
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This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
Adrian Costina
a49eb5853b
ZED, ZC702: Added contraints so that projects can successfully synthesize on linux systems
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For ZC706 Fixed one constraint which was not correct
2014-08-26 16:28:41 +03:00
Istvan Csomortani
f9a67371c0
Zynq Base System: Reset is synchronized to lowest system clock
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System reset (sys_100m_reset) is synchronized to lowest system
clock (FCLK0), via a Processor System Reset module
2014-03-26 17:58:14 +02:00
Rejeesh Kutty
dc44703cf1
zynq/non-zynq: identical signal names and instances
2014-03-17 17:02:03 -04:00
Rejeesh Kutty
f3ae57a53e
global clock and reset names
2014-03-11 09:57:59 -04:00
Rejeesh Kutty
ddac1a8834
added common board files
2014-02-28 21:17:01 -05:00