2 Commits (168e1951eed661ca15eb5e001f27af0812a4d415)

Author	SHA1	Message	Date
Adrian Costina	168e1951ee	library: Add `timescale to modules that are missing it	2019-05-15 15:37:44 +03:00
Lars-Peter Clausen	b3f027fc89	axi_dmac: Add simple register map testbench ... Add a testbench that exercises the basic functionality of the axi_dmac register map module. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2018-05-03 14:49:06 +02:00