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6 Commits (169f38e7d1f081957a6613f8668df80ed6844c8f)

Author SHA1 Message Date
Istvan Csomortani 2293374307 adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs 
The affected projects are:
  - FMCADC2/VC707 - 16Mb
  - FMCADC5/VC707 - 16Mb
  - DAQ2/ZC706  - ADC@1GB and DAC@8Mb
  - DAQ2/KC705  - ADC@4Mb and DAC@4Mb
  - DAQ2/VC707  - ADC@8Mb and DAC@8Mb
  - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb
  - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb
  - DAQ3/ZC706  - ADC@1GB and DAC@8Mb
  - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb
  - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb
  - ADRV9371x/KCU105 - DAC@8Mb
  - ADRV9371x/ZCU102 - DAC@16Mb
 2018-08-21 11:44:05 +03:00
Istvan Csomortani bd8c71c2ec adrv9371x:zcu102: Set DEVICE_TYPE to ultrascale 2018-04-11 15:09:54 +03:00
Michael Hennerich 2e59a70cdd adrv9371: Increase FCLK2 to 200MHz to support max sampling rates 
This fixes an issue seen when using 307.2 MSPS on the Observation RX.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
 2018-01-09 15:20:06 +01:00
Lars-Peter Clausen 46acdadb92 adrv9371x: Set correct transceiver type for UltraScale projects 
Make sure that the axi_adxcvr instances are configured with the same
transceiver type as the util_adxcvr.

This is necessary for software to be able to detect the transceiver type
and support dynamic reconfiguration.

It is also necessary for correct eye scan support in the axi_adxcvr block.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-11-14 14:31:03 +01:00
Lars-Peter Clausen f181e037cc adrv9371x: zcu102: Fix QPLL feedback divider 
The external reference clock runs at 122.88 MHz by default. This means that
the QPLL feedback divider needs to be set to 80 so that the VCO is inside
the locking range (9.8 GHz - 16.375 GHz).

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-11-14 14:31:03 +01:00
AndreiGrozav d05ed29212 adrv9371x_zcu102: Initial commit 2017-08-22 15:48:03 +03:00