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Author SHA1 Message Date
Iulia Moldovan c9a7d4d927 Add copyright and license to .tcl, .ttcl files 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-07-25 15:22:26 +03:00
Iulia Moldovan 28c06d505f Add/edit copyright and license for .v, .sv files 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-07-11 15:17:41 +03:00
AndrDragomir 72378a6d4a projects: Add fmc connection files for eval boards 
Creating a new eval board fmc file:
  - docs: Open FMC_eval_board_template.xlsx
  - follow the instructions on the first sheet
 2022-09-20 14:11:08 +03:00
Iulia Moldovan 961ebe0cc2 projects: Update .v files according to guideline 
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
 2022-06-28 18:06:56 +03:00
Laszlo Nagy f73ed741c9 fmcadc5: Connect link clock to second JESD link layer 2021-02-05 15:24:15 +02:00
IMoldovan 78b2ae02a1 ad9434_fmc,ad9467_fmc,fmcadc5: Update projects to use ad_iobuf, not IOBUF 2020-11-02 16:13:35 +02:00
Istvan Csomortani 019390f9bf block_design: Updates with new reset net variables 2019-06-11 18:13:06 +03:00
Istvan Csomortani 7960b00684 block_design: Update with new clock net variables 
Using the new clock net variables in all Xilinx block designs.
 2019-06-11 18:13:06 +03:00
Laszlo Nagy c37b24d00f fmcadc5: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy 085c0ed0da fmcadc5: remove SYSREF from IOB 
The SYSREF for RX is generated internally,
disable the IOB attribute from it to avoid critical warnings.
 2018-07-26 12:33:25 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Adrian Costina 9c8d4b9bdf fmcadc5: Fix RXCDR_CFG parameter 
The default linux configuration is at lane rates under 6.6G and in LPM mode
 2018-04-11 15:09:54 +03:00
Adrian Costina 62fcaa7836 fmcadc5: Remove xcvr configuration options that don't matter 2018-04-11 15:09:54 +03:00
Adrian Costina 386febaa7e fmcadc5: Allow JESD reset from the ADC core, useful for synchronization 2017-11-29 16:03:00 +02:00
Adrian Costina c07fefcbd7 fmcadc5: Update to the ADI JESD interface 2017-11-20 15:12:47 +02:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files 
Fix a few gramatical error, fix the path of the top level license
files.
 2017-05-29 09:55:41 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files 
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
 2017-05-17 11:52:08 +03:00
Rejeesh Kutty 039ae9ae92 fmcadc5- syntax/port name fixes 2017-05-10 16:30:15 -04:00
Rejeesh Kutty 74c44cf830 axi_fmcadc5- remove pack-driver is too late 2017-05-10 14:33:56 -04:00
Rejeesh Kutty 0e5a24ee7c axi_fmcadc5_sync- raw inputs & constraint fixes 2017-05-08 10:30:51 -04:00
Rejeesh Kutty d29f420ffa axi_fmcadc5_sync: add a calibration signal generation 2017-04-28 11:13:24 -04:00
Rejeesh Kutty 68fc5c89a7 fmcadc5- remove stand alone psync 2017-04-27 15:09:56 -04:00
Rejeesh Kutty 902eaaaf4c fmcadc5- sync updates 2017-04-27 13:26:17 -04:00
Rejeesh Kutty 8fba8295f0 fmcadc5- hdl sync handling 2017-04-25 15:44:40 -04:00
Rejeesh Kutty 8e6dbe1917 fmcadc5/vc707, lpm mode 2017-04-18 12:41:53 -04:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
AndreiGrozav 04a4001dba Ip automatic version update: fmcadc2, fmcadc5 2017-04-12 19:03:16 +03:00
Rejeesh Kutty 19c7b5d340 fmcadc5- move adc fifo settings to system-board 2017-02-27 16:06:39 -05:00
Adrian Costina 040b61de60 fmcadc5: Updated default parameters 2017-02-20 17:13:58 +02:00
Rejeesh Kutty 11b57290f1 fmcadc5- replaced with axi_adxcvr 2016-11-23 16:22:05 -05:00
Adrian Costina 6f0d124861 fmcadc5: Update to Vivado 2016.2 2016-08-30 16:09:28 +03:00
Rejeesh Kutty ce1fed1ce6 dmafifo- adc/dac split 2016-08-16 12:54:39 -04:00
AndreiGrozav 62bd057106 fmcadc5/common: Update common design to 2015.4 2016-04-14 23:01:38 +03:00
Adrian Costina 40fb68dfd5 ad9265, ad9434, ad9467, daq1, daq2, daq3, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1, fmcomms6, fmcomms7, usdrx1: updated common spi module so that spi streaming is possible 2016-03-02 13:39:37 +02:00
Rejeesh Kutty cafc80c829 fmcadc5: add programmable io delay 2015-11-02 12:10:18 -05:00
Rejeesh Kutty 24d76c610a fmcadc5- fix core connections 2015-10-29 16:47:56 -04:00
Rejeesh Kutty cb2bda48c0 fmcadc5- gt/ip updates 2015-10-19 09:31:32 -04:00
Rejeesh Kutty 030485de28 fmcadc5- regulators need a switching ref clock? 2015-10-15 10:46:07 -04:00
Rejeesh Kutty f966f79e5f fmcadc5- regulators need a switching ref clock? 2015-10-15 10:46:07 -04:00
Istvan Csomortani 4f99bdd93f fmcadc5: Update project 
+ Update the JESD IP core for Vivado 2015.2
+ Update the framework for JESD interface
 2015-09-25 19:11:14 +03:00
Lars-Peter Clausen dd79dfdc12 fmcadc5: Drop explicit axi_dmac clock synchronicity configuration 
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-09-18 15:28:03 +02:00
Istvan Csomortani d52308f074 axi_dmac: Change parameter name 2D_TRANSFER 
Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
 2015-08-20 10:14:22 +03:00
Istvan Csomortani 57cfb7cfb1 hdl/library: Update the IP parameters 
The following IP parameters were renamed:

PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
 2015-08-19 14:11:47 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file 
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-06-26 11:07:10 +02:00
Rejeesh Kutty 71b5004b25 projects- drp moved to up-clock domain 2015-06-01 14:57:59 -04:00
Rejeesh Kutty a09075030c fmcadc5: 2014.4 updates 2015-03-23 10:00:46 -04:00
Rejeesh Kutty 0a8fabe874 Merge branch 'hdl_2014_r2' into dev 
Conflicts:
	projects/fmcadc5/common/fmcadc5_bd.tcl
	projects/motcon1_fmc/common/motcon1_fmc_bd.tcl
	projects/motcon1_fmc/zed/system_constr.xdc
	projects/motcon1_fmc/zed/system_top.v
 2014-12-08 11:32:13 -05:00
Rejeesh Kutty 19e4950b72 renamed to match official names 2014-12-08 10:44:15 -05:00