Istvan Csomortani
|
16ee1336c3
|
Makefile: Update make files
|
2016-09-15 11:41:06 +03:00 |
|
Istvan Csomortani
|
3b0c1e02fc
|
axi_dacfifo: Move IP to library/xilinx
|
2016-09-15 11:38:16 +03:00 |
|
Istvan Csomortani
|
3cbbc771a8
|
axi_adcfifo: Move IP to library/xilinx
|
2016-09-15 11:36:47 +03:00 |
Rejeesh Kutty
|
fe133a7c39
|
v2001- parameter defines
|
2016-09-14 15:47:45 -04:00 |
|
Rejeesh Kutty
|
16046a984c
|
alt_serdes- updates
|
2016-09-14 12:05:48 -04:00 |
|
Rejeesh Kutty
|
4a6b554c0a
|
ad_serdes- updates
|
2016-09-14 11:12:53 -04:00 |
Adrian Costina
|
343056b674
|
axi_usb_fx3: Update IP to work with 2016.2
|
2016-09-14 15:40:42 +03:00 |
|
Rejeesh Kutty
|
a0318ae868
|
ad_serdes_clk- syntax errors
|
2016-09-13 14:02:11 -04:00 |
|
Istvan Csomortani
|
734b39a8ed
|
alt_serdes: Fix some issues in the _hw.tcl script
|
2016-09-13 17:42:51 +03:00 |
|
Rejeesh Kutty
|
bced17a16f
|
axi_ad9144- qsys updates
|
2016-09-12 14:57:50 -04:00 |
|
Rejeesh Kutty
|
01b7662e05
|
axi_ad9680- qsys updates
|
2016-09-12 14:57:50 -04:00 |
|
Rejeesh Kutty
|
c6998dd396
|
scripts- altera conduit
|
2016-09-12 14:57:50 -04:00 |
|
Rejeesh Kutty
|
73ebf1225c
|
axi_adxcvr- ip/phy split
|
2016-09-12 14:57:50 -04:00 |
|
Rejeesh Kutty
|
21545ee83f
|
avl_adxcvr- ip/phy split
|
2016-09-12 14:57:50 -04:00 |
|
Rejeesh Kutty
|
8718b7f477
|
avl_adxphy- ip/phy split
|
2016-09-12 14:57:50 -04:00 |
|
Rejeesh Kutty
|
d30ffdb7e9
|
avl_adxcfg- ip/phy split
|
2016-09-12 14:57:50 -04:00 |
|
Rejeesh Kutty
|
9159e31244
|
axi_adxcvr- compile fixes
|
2016-09-12 14:57:50 -04:00 |
|
Rejeesh Kutty
|
5a309d8863
|
avl_adxphy- split
|
2016-09-12 14:57:50 -04:00 |
|
Rejeesh Kutty
|
2a34f9baa8
|
alt-serdes, in & out
|
2016-09-12 11:45:23 -04:00 |
|
Rejeesh Kutty
|
9e0c39a71b
|
alt_serdes_clk- changes
|
2016-09-12 10:30:28 -04:00 |
|
Istvan Csomortani
|
f4be0524b4
|
altera/common: Add SERDES related modules
|
2016-09-09 18:04:41 +03:00 |
|
Istvan Csomortani
|
a183e51a12
|
axi_ad9361: Add parameter R1_MODE_EN
R1_MODE_EN can disable the second I/Q channel of the core. This way
the user can save resources by cutting down the size of the core.
|
2016-09-09 16:34:11 +03:00 |
|
Istvan Csomortani
|
e42206e510
|
axi_ad9361: Add a TDD enable/disable parameter
|
2016-09-09 14:38:28 +03:00 |
|
Istvan Csomortani
|
be41a8bcaa
|
axi_ad9361: Delete debug ports of the tdd module
|
2016-09-09 14:38:28 +03:00 |
AndreiGrozav
|
bbcf2a3ec3
|
axi_ad9434/axi_ad9434_constr: Change constraint file to resolve critical warning
|
2016-09-01 17:16:59 +03:00 |
|
Rejeesh Kutty
|
4ae084ee32
|
avl_adxcvr- compile fixes
|
2016-09-01 10:06:28 -04:00 |
|
Rejeesh Kutty
|
5544e3cf10
|
axi_adxcvr- compile fixes
|
2016-09-01 10:06:28 -04:00 |
|
Rejeesh Kutty
|
230f1526c0
|
avl_adxcfg- compile fixes
|
2016-09-01 10:06:28 -04:00 |
|
Rejeesh Kutty
|
b7ea2efa87
|
altera- xcvr cores
|
2016-08-29 15:18:48 -04:00 |
|
Rejeesh Kutty
|
9799599eee
|
library/ad9361- add dac clk sel
|
2016-08-26 10:31:00 -04:00 |
|
Rejeesh Kutty
|
74bc498a6d
|
library/common- added dac clock select
|
2016-08-26 10:31:00 -04:00 |
Shrutika Redkar
|
10b9a0e52f
|
upadated xcvr ips
|
2016-08-17 15:51:55 -04:00 |
|
Adrian Costina
|
6a8ca8107a
|
common: Added common ad_dcfilter stub for altera.
|
2016-08-16 17:37:16 +03:00 |
|
Rejeesh Kutty
|
e754f0a46a
|
up_axi- writes dropped by delayed w-responses
|
2016-08-14 11:21:19 -04:00 |
|
Rejeesh Kutty
|
3427965cd2
|
adxcvr- add u-gth bufg
|
2016-08-11 10:00:41 -04:00 |
|
Rejeesh Kutty
|
bb9cb86f34
|
adc/dac- fifo constraints
|
2016-08-11 10:00:41 -04:00 |
|
Shrutika Redkar
|
829e4155ca
|
modified transceiver configuration files
|
2016-08-10 14:59:38 -04:00 |
|
Shrutika Redkar
|
b8f4e1c0aa
|
updated 9680 hdl files(to resolve a critical warning)
|
2016-08-10 14:50:31 -04:00 |
|
Istvan Csomortani
|
ccf1c56b33
|
util_upack: Patch up the description of Altera IP
|
2016-08-08 16:39:56 +03:00 |
|
Istvan Csomortani
|
e9ac4a5a0e
|
util_rfifo: Patch up the description of Altera IP
|
2016-08-08 16:39:25 +03:00 |
|
Istvan Csomortani
|
0cd608a7e2
|
lib_refactoring: Update Make files
|
2016-08-08 16:38:38 +03:00 |
|
Istvan Csomortani
|
aad8c265bc
|
lib_refactoring: Fix path for CMOS sources
|
2016-08-08 15:07:54 +03:00 |
|
Istvan Csomortani
|
1d33d7d7ee
|
lib_refactoring: Move the CMOS interface modules to ~/library/xilinx/common
|
2016-08-08 15:07:42 +03:00 |
|
Istvan Csomortani
|
df36902713
|
lib_refactoring: Fix path of the IO macros
|
2016-08-08 15:07:19 +03:00 |
|
Istvan Csomortani
|
90ac7b7ac9
|
lib_refactoring: Move all Altera module to library/altera/common
Move all Altera modules to library/altera/common, delete the
deprecated wrapper files
|
2016-08-08 15:07:01 +03:00 |
|
Istvan Csomortani
|
cb9af99c5d
|
lib_refactoring: Add ad_mul.v for Altera
|
2016-08-08 15:06:48 +03:00 |
|
Istvan Csomortani
|
b806fa3b42
|
lib_refactoring: Move all the Xilinx common modules to library/xilinx/common
|
2016-08-08 15:06:10 +03:00 |
|
Adrian Costina
|
5faf4c4976
|
cleanup: Don't need Makefiles specific to xilinx/altera libraries. Top Makefile covers them
|
2016-08-05 16:27:52 +03:00 |
|
Adrian Costina
|
d60bce654c
|
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
|
2016-08-05 15:16:04 +03:00 |
|
Rejeesh Kutty
|
cb23ba8bb7
|
make- script needs update
|
2016-08-04 14:17:04 -04:00 |