Commit Graph

33 Commits (1746701d45e5f38221f7b3b3f23219abc80fbd5d)

Author SHA1 Message Date
AndreiGrozav 59c726ecbe fmcjesdadc1: Updated common design to 2015.4 2016-03-16 10:14:06 +02:00
Adrian Costina 89f7aadfb1 fmcjesdadc1: A5GT, connected xcvr_rxt_cntrl reset input to the axi_jesd_xcvr reset output
This will allow for the transceivers to be reset by the axi_jesd_xcvr core
2016-02-23 11:31:07 +02:00
Adrian Costina 0f37dd6424 fmcjesdadc1: Fixed project
- changed system_project.tcl so that all base designs to be included
- changed DMA properties to take into consideration the new parameter names
- changed reset bridges to asynchronous
- increased maximum burst size of the DMA bridge
- changed the data_width of the memory bus to 256, as with 512 timing violations may occur
- changed base addresses for the base system to be the same as in the previous release
2016-02-19 14:09:57 +02:00
Adrian Costina 9281eb2c33 fmcjesdadc1: Updated common altera design 2015-11-24 15:38:58 +02:00
Adrian Costina 2ed161628d fmcjesdadc1: Updated project to 2015.2.1
- updated to the new jesd framework
- added cpack core
2015-09-24 19:12:40 +03:00
Lars-Peter Clausen 7e2255f4d9 fmcjesdadc1: Drop explicit axi_dmac clock synchronicity configuration
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:05 +02:00
Istvan Csomortani d52308f074 axi_dmac: Change parameter name 2D_TRANSFER
Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 10:14:22 +03:00
Istvan Csomortani 57cfb7cfb1 hdl/library: Update the IP parameters
The following IP parameters were renamed:

PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
Adrian Costina 36f71ea59b fmcjesdadc1: common altera, fixed dmac configuration and connection. Connected reset for cpack 2015-07-28 12:33:24 +03:00
Rejeesh Kutty 289e73660b removed- xcvr is now part of qsys 2015-07-23 15:26:51 -04:00
Rejeesh Kutty d8e2196c75 fmcjesdadc1- board qsys 2015-07-22 15:44:04 -04:00
Rejeesh Kutty d66387f482 fmcjesdadc1- board qsys 2015-07-22 15:23:39 -04:00
Rejeesh Kutty 4e99a2cb01 xcvr: remove signal tap 2015-07-16 08:09:56 -04:00
Rejeesh Kutty 2d8fa2024b fmcjesdadc1/a5gt: split xcvr cores 2015-07-15 09:44:52 -04:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Rejeesh Kutty 71b5004b25 projects- drp moved to up-clock domain 2015-06-01 14:57:59 -04:00
Adrian Costina e332fa01c8 ad6676evb, daq2, fmcadc2, fmcjesdadc1, usdrx1: Updated jesd reset connection 2015-04-30 12:11:46 +03:00
Adrian Costina c7e4ba5083 fmcjesdadc1: Updated KC705 to the latest flow 2015-03-30 18:07:47 +03:00
Adrian Costina ccf0542218 fmcjesdadc1: Connected constant 0 to unconnected inputs 2015-03-26 12:08:14 +02:00
Adrian Costina d418c9f9b1 fmcjesdadc1: Updated project to new flow. Updated ZC706 design 2015-03-24 10:38:14 +02:00
Michael Hennerich 138e789fb6 projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl: Fix interrupts
sys_concat_intc: don't reset NUM_PORTS to 6

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-09 17:38:16 +01:00
Istvan Csomortani b0f571ce0c fmcjesdadc1: Fix parameter lane number for GT core 2014-11-21 19:17:29 +02:00
Istvan Csomortani 57137df018 fmcjesdadc1_zc706: Interrupt update 2014-11-03 13:02:09 +02:00
Istvan Csomortani 17675863e0 all_projects: Fix the interrupt connections to preserve IRQ layout 2014-10-22 11:48:08 +03:00
Istvan Csomortani 02802644bf fmcjesdadc1: Fix a few warning and issue with ILA
+ GPIO width is 15
+ Fix ILA core
2014-10-15 15:37:05 +03:00
Istvan Csomortani 6f77af4aff fmcjesdadc1: Upgrade project to 2014.2 2014-10-09 18:55:27 +03:00
Istvan Csomortani 2ce7695bf7 fmcjesdadc1: Initial commit of VC707 version 2014-09-01 18:47:01 +03:00
Istvan Csomortani 9a80fec4e4 fmcjesdadc1: Delete trailing whitespaces 2014-09-01 18:45:20 +03:00
Rejeesh Kutty 5f21f54463 fmcjesdadc1: zc706 version 2014-08-25 14:28:57 -04:00
Rejeesh Kutty 76ffb939e5 zc706: ad9625 copy 2014-08-22 11:24:24 -04:00
Rejeesh Kutty 96969079ce a5soc: fixes for 14.0 and spi conflicts 2014-08-11 16:46:37 -04:00
Rejeesh Kutty 60dd14bcdb a5soc: removed jtag master control 2014-07-01 12:27:37 -04:00
Rejeesh Kutty 0d678b89ed altera a5gt fmcjesdadc1 setup 2014-04-01 11:46:37 -04:00