2 Commits (17c749962c9edcbb0011791334fecf235bc38990)

Author	SHA1	Message	Date
Istvan Csomortani	e3ea51ade3	avl_dacfifo: Refactor the fifo ... + Build both the read and write logic around an FSM + Consistent naming of registers and wires + Add support for burst lenghts higher than one, current burst lenght is 64 + Fix all the bugs, and make it work (first bring up with adrv9371x/a10soc)	2017-10-31 14:30:06 +00:00
Istvan Csomortani	700ed156ab	[axi|avl]_dacfifo: Create a separate bypass module for altera/xilinx	2017-09-25 08:56:40 +01:00