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12 Commits (19015a81998345243def9d9c6ce21651380b20d0)

Author SHA1 Message Date
Istvan Csomortani ac2e5a9dac constraints: Update constraints 
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
 2017-02-24 13:43:32 +02:00
Istvan Csomortani 1156aeac16 ad_sysref_gen: Update SYSREF related constraints 2016-12-19 18:07:05 +02:00
Istvan Csomortani 0c42e04bc3 fmcadc2: Integrate ad_sysref_gen into the project 2016-12-19 12:16:05 +00:00
AndreiGrozav aff45eae5f fmcadc2: xcvr updates 2016-11-21 18:45:38 +02:00
Adrian Costina 377461e0d4 Merge branch 'hdl_2015_r2' into dev 2016-02-19 14:15:27 +02:00
Rejeesh Kutty ce760eb691 fmcadc2- add adf4355 access 2016-02-18 16:17:33 -05:00
Adrian Costina 9cd0378003 fmcadc2: Added clock constraint for the ADC path 2016-01-22 15:44:04 +02:00
Adrian Costina e764f54426 fmcadc2: Updated ZC706 project 2015-09-25 17:26:54 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file 
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-06-26 11:07:10 +02:00
Istvan Csomortani 8b5d1a8693 fmcadc2: Connect the second CS line for the external SPI interface 2015-04-15 19:08:17 +03:00
Rejeesh Kutty 01de3e7984 fmcadc2: 2014.4 updates 2015-03-19 13:22:30 -04:00
Rejeesh Kutty 19e4950b72 renamed to match official names 2014-12-08 10:44:15 -05:00