c152b60137
ad_mem_asym: Improve the implementation of the asymmetric RAM
...
Because the read interface got a read enable port too, update all the
ad_mem_asym instances.
2018-08-06 17:29:05 +03:00
97800745db
util_dacfifo_bypass: Update comments
2018-06-11 17:26:04 +03:00
5d3b2b1550
[axi|avl]_dacfifo: Fix the util_dacfifo_module
...
Fix the read side of the CDC data FIFO. The read address generation did not
function correctly.
Redesign the read side of the FIFO, and make sure that it becomes empty after
the DMA transfer ends; and never get stock in a cyclic mode.
2018-06-11 17:26:04 +03:00
b338b30964
axi_dacfifo: Cosmetic changes in util_dacfifo_bypass
2018-06-11 17:26:04 +03:00
04ff8bbff4
util_dacfifo: Fix gray coder/decoder
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Make the gray coder/decoder's data width parameterizable.
2018-06-11 17:26:04 +03:00
425e803364
license: Fix a spelling mistake
2018-04-11 15:09:54 +03:00
700ed156ab
[axi|avl]_dacfifo: Create a separate bypass module for altera/xilinx
2017-09-25 08:56:40 +01:00
Istvan Csomortani