1a11e28821
ad9361- dac data path split
2016-09-23 16:13:46 -04:00
6735333aea
common- dac data path split
2016-09-23 16:13:24 -04:00
6837143110
library/ adc parameter changes
2016-09-23 13:44:47 -04:00
7be6168b2e
ad9361- adc data path split
2016-09-23 13:42:14 -04:00
8729af1b91
common- adc- data path disable split
2016-09-23 13:40:35 -04:00
78f7384150
ad9361- vivado synthesis warnings fix
2016-09-22 13:41:18 -04:00
2b6eb1d65e
up_drp: Revert some bit locations
...
Linuxe drivers are checking the drp_locked status even if the
core does not contains a clock generation/managment module. To
not break all the designs, revert all the status and control bits to
there old locations.
2016-09-22 16:32:42 +03:00
21b5e9c634
hdlmake- updates
2016-09-21 11:56:03 -04:00
0def596b43
axi_xcvrlb- updates
2016-09-21 11:04:22 -04:00
d497a7b0ae
axi_xcvrlb- constraints
2016-09-21 11:04:22 -04:00
a21b9fe8ff
up_drp: Fix up_drp_wr
2016-09-21 17:55:58 +03:00
64cd7dc002
axi_ad9122: Update core to the new DRP interface
2016-09-21 16:09:55 +03:00
bae839acd4
axi_ad9739a: Update core to the new DRP interface
2016-09-21 15:23:08 +03:00
781702c1b9
axi_ad9434: Update the core to the new DRP interface
2016-09-21 15:12:59 +03:00
913eafed48
up_drp : Update the DRP interface to support Altera platforms
2016-09-21 15:00:45 +03:00
10408b8c88
up_tdd_cntrl: Set PCORE version to 1.00.a
2016-09-21 10:27:28 +03:00
1860d72df6
axi_xcvrlb- updates
2016-09-19 12:39:59 -04:00
5592c2780e
axi_xcvrlb- loopback version
2016-09-19 12:39:59 -04:00
38f1521861
xilinx/ad_serdes_in : Fix some typos
2016-09-19 16:02:52 +03:00
ff0f659a33
xilinx/ad_serdes_clk : Rename parameter MMCM_DEVICE_TYPE to DEVICE_TYPE
2016-09-19 16:02:06 +03:00
2159f78c80
axi_ad9361: Delete invalid assignment of a generated wire
2016-09-16 17:38:08 +03:00
6510f92c12
ad_serdes : Cosmetic changes
2016-09-16 14:45:39 +03:00
13a35f7a2a
altera/ad_serdes_clk: The IO_PLL reset is active heigh
2016-09-16 14:20:39 +03:00
858ea09048
altera/ad_serdes_in: Fix some typos
2016-09-16 10:56:16 +03:00
a2d15acb89
ad_serdes- altera/xilinx sync
2016-09-15 13:33:55 -04:00
63696c1a28
alt_serdes- data-width parameter
2016-09-15 11:12:18 -04:00
02dfd2d2e2
altera/ad_serdes_out- sample transmit order
2016-09-15 10:28:34 -04:00
5986f45cba
altera/ad_serdes_out- updates
2016-09-15 09:38:11 -04:00
16ee1336c3
Makefile: Update make files
2016-09-15 11:41:06 +03:00
3b0c1e02fc
axi_dacfifo: Move IP to library/xilinx
2016-09-15 11:38:16 +03:00
3cbbc771a8
axi_adcfifo: Move IP to library/xilinx
2016-09-15 11:36:47 +03:00
fe133a7c39
v2001- parameter defines
2016-09-14 15:47:45 -04:00
16046a984c
alt_serdes- updates
2016-09-14 12:05:48 -04:00
4a6b554c0a
ad_serdes- updates
2016-09-14 11:12:53 -04:00
343056b674
axi_usb_fx3: Update IP to work with 2016.2
2016-09-14 15:40:42 +03:00
a0318ae868
ad_serdes_clk- syntax errors
2016-09-13 14:02:11 -04:00
734b39a8ed
alt_serdes: Fix some issues in the _hw.tcl script
2016-09-13 17:42:51 +03:00
bced17a16f
axi_ad9144- qsys updates
2016-09-12 14:57:50 -04:00
01b7662e05
axi_ad9680- qsys updates
2016-09-12 14:57:50 -04:00
c6998dd396
scripts- altera conduit
2016-09-12 14:57:50 -04:00
73ebf1225c
axi_adxcvr- ip/phy split
2016-09-12 14:57:50 -04:00
21545ee83f
avl_adxcvr- ip/phy split
2016-09-12 14:57:50 -04:00
8718b7f477
avl_adxphy- ip/phy split
2016-09-12 14:57:50 -04:00
d30ffdb7e9
avl_adxcfg- ip/phy split
2016-09-12 14:57:50 -04:00
9159e31244
axi_adxcvr- compile fixes
2016-09-12 14:57:50 -04:00
5a309d8863
avl_adxphy- split
2016-09-12 14:57:50 -04:00
2a34f9baa8
alt-serdes, in & out
2016-09-12 11:45:23 -04:00
9e0c39a71b
alt_serdes_clk- changes
2016-09-12 10:30:28 -04:00
f4be0524b4
altera/common: Add SERDES related modules
2016-09-09 18:04:41 +03:00
a183e51a12
axi_ad9361: Add parameter R1_MODE_EN
...
R1_MODE_EN can disable the second I/Q channel of the core. This way
the user can save resources by cutting down the size of the core.
2016-09-09 16:34:11 +03:00
Rejeesh Kutty
Istvan Csomortani
Dragos Bogdan
AndreiGrozav
Adrian Costina