Commit Graph

54 Commits (1bd444b47f0196a8a183447680e7d07aeaed5bc9)

Author SHA1 Message Date
Adrian Costina 8b76c34dea scripts: Created ADI_POWER_OPTIMIZATION parameter for enabling power optimizations in the implementation stage 2017-04-18 12:17:40 +02:00
Rejeesh Kutty 6d2b3bc1c7 adi_project- try something simple first 2017-04-11 14:27:35 -04:00
Rejeesh Kutty 879ed64bb6 compression flag changes 2017-02-22 15:15:53 -05:00
Rejeesh Kutty f43248c2bc common/pzsdr*- removed 2016-11-18 11:32:43 -05:00
Rejeesh Kutty 33f9ed33c7 projects- ultrascale+ 2016-09-30 11:55:10 -04:00
Rejeesh Kutty 67bf8f8e78 scripts- fix path and device defaults and override 2016-08-19 15:56:07 -04:00
Adrian Costina 452d4706d3 kcu105: Update base project to 2015.4.2
- change part to revision 1.1 of the board
2016-08-09 10:19:36 +03:00
Shrutika Redkar 6ffe59728b hdl-vivado-2016.2- update 2016-07-28 13:44:57 -04:00
Lars-Peter Clausen 44d9f98e12 adi_project.pl: Fix ADI_NO_BITSTREAM_COMPRESSION detection logic
Only enable bitstream compression only if both the
ADI_NO_BITSTREAM_COMPRESSION environment and TCL variable are not set.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-07-14 10:44:42 +02:00
Lars-Peter Clausen 62c7114d77 Enable bitstream compression for Xilinx projects
Enabling bitstream compression reduces the size of the generated bitstream.

This means on one hand it will consume less storage, which is especially
useful for the BOOT partition of the ADI images where we store BOOT.BIN
files for all supported platforms.

On the other hand a smaller bitstream is faster to load from the storage
medium and it is also faster to program to the FPGA. So it reduces the
overall boot time as well.

The only downside of bitstream compression is that the bitstream size is no
longer constant, but depends on the actual design and resource utilization.
This will not work with bootloaders that expect a fixed size.

When building a bitstream using the tcl scripts bitstream compression can
be disabled by setting the ADI_NO_BITSTREAM_COMPRESSION environment
variable.

Initial tests show a reduction of a round 50% in size for most ADI
projects.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-07-14 10:16:15 +02:00
Rejeesh Kutty 16e3a0e569 zcu102- updates 2016-05-10 15:40:41 -04:00
AndreiGrozav 679d471d75 Merge branch 'hdl_2016_r1' into dev
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
AndreiGrozav 71be9519ec adi_project.tcl: Updated to 2015.4 2016-03-15 15:03:50 +02:00
Rejeesh Kutty b147e9c94a pzsdr1- updates 2016-02-02 12:33:01 -05:00
Rejeesh Kutty bcac3eef4d pzsdr1- initial commit 2016-01-25 16:07:33 -05:00
Lars-Peter Clausen 51d20b1a61 adi_project.tcl: Add MicroZed support
Handle the projects for the MicroZed and set up the FPGA part accordingly.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 20:32:26 +01:00
Istvan Csomortani ef9bdf6ec9 adi_project: Regenerate the layout of the IP Integrator subsystem design. 2015-11-09 11:01:10 +02:00
Adrian Costina afc4274ee3 common scripts: Changed the resulting hdf file to system_top_bad_timing, if design doesn't meet timing. 2015-11-06 16:01:19 +02:00
Adrian Costina 0c7c0f2cd8 common scripts: Change the name of the generated HDF if the design doesn't meet timing 2015-11-05 18:41:51 +02:00
Istvan Csomortani c83239b014 fmcomms2/zc706pr: Update PR design
+ Add system_top.v to design
+ Add pr specific constraints
2015-10-09 13:23:42 +03:00
Rejeesh Kutty 48af5f29de rfsom renamed to pzsdr 2015-09-18 11:19:50 -04:00
Istvan Csomortani 971e3395e7 projects/scripts: Update board part names.
Property 'board' is deprecated for object type 'project', 'board_part' is used. Update the 'board_part' property names for all Xilinx development boards.
2015-08-25 10:19:57 +03:00
Istvan Csomortani 0dfb3e2019 tcl_scripts: Update Vivado version number to 2015.2.1 2015-08-20 10:50:52 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Rejeesh Kutty e489090fbb scripts- initialize prcfg list 2015-05-04 12:34:19 -04:00
Istvan Csomortani e7a0da9089 fmcomms2 : Verify the existence of the PR license
The fmcomms2 runs by default on PR mode, if the project script does not find a PR license, will implement just the default mode.
2015-05-04 15:12:38 +03:00
Rejeesh Kutty 4bb26caa13 itx045: default install 2015-05-01 16:19:10 -04:00
Rejeesh Kutty 26fb85583b adi_project- prefix directory for gitignore & make clean 2015-05-01 13:18:12 -04:00
Rejeesh Kutty 0dc4c9cda9 adi_project: added partial reconfiguration 2015-05-01 12:21:59 -04:00
Rejeesh Kutty da5b136f5a daq2+base: board tcl updates 2015-03-05 10:56:36 -05:00
Rejeesh Kutty 4f918cdce9 2014.4.1 ultrascale updates 2015-02-26 16:10:57 -05:00
Rejeesh Kutty b9d16a7eb1 scripts: renaming board parameters 2015-02-20 09:12:30 -05:00
Rejeesh Kutty 024d9e7309 replace export hardware -- hwdef/sysdef 2015-01-13 13:40:21 -05:00
Rejeesh Kutty 43037a42eb scripts: 2014.4 update 2014-12-23 14:03:51 -05:00
Lars-Peter Clausen 84052ad437 Add Vivado version check to adi_project_create
The scripts generating the projects files typically only work correctly with
one specific version of Vivado. If a incorrect version is used the script
may fail at some point with a cryptic error message or may not fail but
create a bitstream that is not working as expected, e.g. unconnected
signals, etc. This patch adds a version check to adi_project_create that
will error out early on stating that the wrong version of Vivado was used
and which is the right version to use.

By default the required version will be the version that is required by the
common scripts. Individual projects can overwrite the required version by
setting the REQUIRED_VIVADO_VERSION variable to the required version or can
bypass the version check completely by setting the IGNORE_VERSION_CHECK
variable to 1.

Callers of the script can also disable the version check by setting the
ADI_IGNORE_VERSION_CHECK environment variable.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-11-26 10:46:34 +01:00
Istvan Csomortani bbf1f0c156 adi_project: Add board definition for mitx045 2014-11-18 10:05:57 +02:00
Istvan Csomortani eaacd4d49a adi_project.tcl: Fix message severity (working solution)
Need to define the default/initial severity too.
2014-11-13 18:55:43 +02:00
Istvan Csomortani 4bcf338e9b adi_project.tcl : Fix message severity
When message severity is set to 'error', need to do it quiet, other way the tool will stop after synthesis, complaining for previous errors.
2014-11-13 16:33:47 +02:00
Istvan Csomortani 776a396141 adi_project.tcl: Add new message severity definition
Set "Parameter does not exist!" message severity to error.
2014-11-11 19:20:40 +02:00
Rejeesh Kutty 54f341fad8 scripts: sdk export before timing check 2014-10-27 09:59:52 -04:00
Rejeesh Kutty 4494998940 scripts: ignore another variant of reset warning 2014-10-27 09:59:51 -04:00
Rejeesh Kutty f3c9627cae adi_project: demote reset warnings to info 2014-10-17 14:38:13 -04:00
Rejeesh Kutty 0aed11fa6c adi_project: demote useless warnings 2014-10-15 14:50:54 -04:00
Istvan Csomortani f2cd7626f5 adi_project : ZC706 board name changed on 2014.2 2014-09-22 17:33:49 +03:00
Rejeesh Kutty 57bb3705f2 zc706-plddr3: read changes to lower dma clock 2014-06-25 09:20:58 -04:00
Adrian Costina c52327d0c6 common,adv7511: Added mitx045 platform. 2014-06-02 11:08:03 +03:00
Rejeesh Kutty 51c0ee1e20 ml605: tcl updates 2014-05-06 09:29:21 -04:00
Rejeesh Kutty ef60cce15e kcu105: added 2014-04-30 14:41:40 -04:00
Istvan Csomortani 5b0e37b97a adi_project.tcl : Modify implementation strategy
- Change implementation strategy to Performance Explore.
	  At some projects, this could prevent timing issues, it not
	  increase the overall implementation time in a dramatic way.
2014-04-07 15:02:38 +03:00
Adrian Costina 698e9f4757 Added phys_opt_design step for fixing timing
The FMCOMMS1 meets timing on ZED/ZC702 only if the phys_opt_design step
is part of the implmentation flow, with the Explore argument.
"This step performs physical optimizations such as timing-driven
replicaiton of high fanouts nets to improve timing results"
2014-03-19 16:42:44 +02:00