111adac825
axi_usb_fx3: Updated core
...
- trig signal will reset state machine
- slrd_n delay will be absorbed by the axi_usb_fx3_if module, when Xilinx DMA is not ready to receive data during a packet
- fx32dma_eop signals when the FX3 DMA buffer should be empty. slrd_n set high and sloe_n set low for another two clock cycles
- eot_fx32dma signals the interface that the packet has been fully transfered. No need for watermark signals
- added length_fx32dma and length_dma2fx3 as requested
2016-10-10 10:33:37 +03:00
ffaf78665f
daq2- xcvr procedures
2016-10-06 14:44:20 -04:00
3b55822db3
daq2- xcvr connect
2016-10-06 14:09:27 -04:00
721ee98a06
zcu102- misc fixes
2016-10-06 10:18:14 -04:00
8965bcffb7
make: Update make files for DAQ3
2016-10-06 10:27:00 +03:00
9ace02a227
daq3/a10gx: Update project to the new GT framework
2016-10-06 10:25:25 +03:00
58c4abd8af
daq3/kcu105: Update project to the new GT framework
2016-10-06 10:23:52 +03:00
ca4dca87e2
daq2- updates
2016-10-05 14:02:59 -04:00
baabe20766
common/zcu102- spi connections & clock
2016-10-05 14:01:59 -04:00
39fdf11ef3
util_adxcvr- rx/tx clocks
2016-10-05 13:53:02 -04:00
7ec93ce8e0
util_adxcvr: Fix some typo
...
GTHE4_CHANNEL is instantiated in case of XCVR_TYPE == 2
2016-10-05 17:42:12 +03:00
4f587d2e48
util_adxcvr: Delete trailing whitespaces
2016-10-05 17:41:40 +03:00
bab9b2df0b
daq3/zc706: Update project with the new transceiver modules
2016-10-05 17:41:25 +03:00
1b9d2d434c
axi_ad9361_tdd: Delete unused register
2016-10-05 17:41:08 +03:00
c196b5bf68
ad6676evb: VC707, fixed system top gpio_bd datawidth
2016-10-05 15:50:43 +03:00
ddceff2b5c
axi_usb_fx3: Updated header/footer signature
2016-10-04 16:11:24 +03:00
48dd4880a3
util_adxcvr- ultrascale+ initial commit
2016-10-03 16:11:45 -04:00
0e8551545c
util_adxcvr- ultrascale+ initial commit
2016-10-03 16:11:45 -04:00
b4652650e4
util_adxcvr- xcvr_type parameter
2016-10-03 16:11:45 -04:00
63ddcf1e26
util_adxcvr- synthesis warnings fix
2016-10-03 16:11:45 -04:00
8e0dc859af
axi_usb_fx3: Update
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- added 1 clock delay for slrd_n signal
- rearrange databytes
2016-10-03 15:17:01 +03:00
43b3761b80
axi_ad9361: Flop the tx and rx valid
2016-10-03 12:24:04 +03:00
8e25bc01b3
all: Change tab to double space
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Occasional file parsing and restructuring become a pain, if tabs exists
in code. General rule of the repos is tab always a double space.
2016-10-01 18:13:42 +03:00
0208335ef3
hdlmake- updates
2016-09-30 13:20:22 -04:00
27c9bdddb6
daq2/zcu102- 2016.2 updates
2016-09-30 11:55:10 -04:00
8e1034946f
fmcomms2/zcu102- 2016.2 updates
2016-09-30 11:55:10 -04:00
9afff7ae60
common/zcu102- 2016.2 updates
2016-09-30 11:55:10 -04:00
33f9ed33c7
projects- ultrascale+
2016-09-30 11:55:10 -04:00
6b956066ef
xilinx/ad_lvds*- ultrascale+
2016-09-30 11:55:10 -04:00
e9105faae1
library/scripts- add beta devices
2016-09-30 11:55:10 -04:00
0ded52d8f6
daq2/zcu102- kcu105 copy
2016-09-30 11:55:10 -04:00
c072c2f89a
util_clkdiv: Add IP
2016-09-30 17:13:51 +03:00
7290bcc81a
hdlmake- updates
2016-09-29 11:50:58 -04:00
4950c6c773
adrv9371x - xcvr updates
2016-09-29 11:50:58 -04:00
4a5b7fc723
scripts- reconnect added
2016-09-29 11:50:58 -04:00
ffec95f220
ad9371- xcvr updates
2016-09-29 11:50:58 -04:00
e40311eee9
adrv9371x: A10soc, connected DMAs through 128 bit SDRAM0 port at 175MHz
2016-09-29 09:14:37 +01:00
b4fac96aad
axi_ad9361- independent disables
2016-09-28 15:45:27 -04:00
f7fb3ccaca
axi_ad9361: Change the data path gating
...
Bring up the datapath gating from the TDD controller module.
2016-09-28 16:36:13 +03:00
df485d7878
axi_ad9684: Fix the PN9 PRBS sequence monitor
2016-09-28 10:47:16 +03:00
4239f64125
dacfifo- board pin warnings
2016-09-27 14:49:20 -04:00
9defccef70
dacfifo- axi address map fixes
2016-09-27 14:48:23 -04:00
c98e2e95dd
ad9162- xcvr updates
2016-09-26 15:21:45 -04:00
692cb10fb2
ad9625- xcvr updates
2016-09-26 15:21:11 -04:00
751a66eb72
plddr3/zc706- board pin warning
2016-09-26 15:20:37 -04:00
79b9e21be8
board- xcvr procedure
2016-09-26 15:20:18 -04:00
8314efd4e9
fmcomms11- xcvr updates
2016-09-26 15:19:29 -04:00
7fd9280cbf
fmcomms11- xcvr updates
2016-09-26 15:19:05 -04:00
ad16aec101
axi_ad9684: Fix SERDES modules
2016-09-26 11:14:35 +03:00
f5809b8817
adrv9371x: a10soc, added adcfifos; connected the new reset to all peripherals; used the new f2sdram1 port
2016-09-24 10:09:05 +03:00
Adrian Costina
Rejeesh Kutty
Istvan Csomortani