Commit Graph

860 Commits (1c32894333cff47197ea7586063265355aece05f)

Author SHA1 Message Date
Rejeesh Kutty 1c32894333 fmcomms2: intrs within ipi 2015-03-12 15:58:55 -04:00
Rejeesh Kutty 6e5186aa2d fmcomms2: intrs within ipi 2015-03-12 15:58:49 -04:00
Rejeesh Kutty 06f6c58e8b fmcomms2: intrs within ipi 2015-03-12 15:58:44 -04:00
Rejeesh Kutty dcce7f8c75 fmcomms2: intrs within ipi 2015-03-12 15:58:37 -04:00
Rejeesh Kutty 28be02406c fmcomms2: intrs within ipi 2015-03-12 15:57:35 -04:00
Rejeesh Kutty f3188b917b common-base-designs: add intr net names 2015-03-12 15:56:31 -04:00
Rejeesh Kutty 3654be4766 common-base-designs: add intr net names 2015-03-12 15:56:25 -04:00
Rejeesh Kutty c1dc93e2c7 common-base-designs: add intr net names 2015-03-12 15:56:15 -04:00
Rejeesh Kutty 91c87b8438 common-base-designs: add intr net names 2015-03-12 15:56:06 -04:00
Rejeesh Kutty 63a390af49 common-base-designs: add intr net names 2015-03-12 15:55:59 -04:00
Rejeesh Kutty f3c41cd9aa common-base-designs: add intr net names 2015-03-12 15:55:50 -04:00
Rejeesh Kutty 8456523084 common-base-designs: add intr net names 2015-03-12 15:55:41 -04:00
Adrian Costina 68224f82de motcon2_fmc: Updated design
- separated clocks for ethernet and other cores in the design
- removed constraints that were not needed
2015-03-12 16:57:59 +02:00
Adrian Costina 27afec5f9e utiil_gmii_to_rgmii: registerd Rx/ Tx paths. Changed RX clock buffers to a single BUFG 2015-03-12 16:57:52 +02:00
Adrian Costina 49f50829fa axi_i2s_adi: Fixed pins directions 2015-03-12 16:57:45 +02:00
Rejeesh Kutty 21f884e346 kc705/vc707: intr sensitivity fix 2015-03-11 15:03:43 -04:00
Rejeesh Kutty ad105b9c54 kc705/vc707: intr sensitivity fix 2015-03-11 15:03:35 -04:00
Istvan Csomortani c92446cee0 ad9467_fmc: Fix port names at ILA logic
In the version 2014.2 the output port of a constant module was changed from 'const' to 'dout'.
This commit fix the non working ILA.
2015-03-11 12:54:12 +02:00
Adrian Costina 46271a7620 motcon2_fmc: added xadc, added constraints for several IP internal clocks 2015-03-02 16:44:42 +02:00
Adrian Costina fe9601643d Merge branch 'hdl_2014_r2' 2015-02-24 15:17:59 +02:00
Adrian Costina 12d8461159 motcon2_fmc: Updated constraint files and fixed reset connection 2015-02-24 12:14:04 +02:00
Lars-Peter Clausen 9c04491e1b fmcomms1: Add extra AXI slice on ADC DMA path
Add a extra AXI slice on the ADC DMA data path to the HP interconnect to
improve the timing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-20 16:38:40 +01:00
Adrian Costina 0be3364dc2 motcon2_fmc: Added system_project.tcl to the project 2015-02-20 16:34:58 +02:00
Adrian Costina 6cd7c51f60 removed motcon1_fmc project, as the new motor control cores are not backward compatible 2015-02-20 16:17:03 +02:00
Adrian Costina 1b19a1b78a Motcon2 initial commit 2015-02-20 16:15:01 +02:00
Adrian Costina cf456caa0e util_gmii_to_rgmii: Gmii to RGMII converter for the motcon2 project 2015-02-20 16:13:54 +02:00
Adrian Costina a81bc7e463 Motor control cores updated for motcon2 2015-02-20 16:12:11 +02:00
Lars-Peter Clausen 277161c143 axi_dmac: Correctly handle shutdown for the request splitter
We need to make sure to not prematurely de-assert the s_valid signal for the
request splitter when disabling the DMAC. Otherwise it is possible that
under certain conditions the DMAC is disabled with a partially accepted
request and when it is enabled again it will continue in an inconsistent
state which can lead to transfer corruption or pipeline stalls.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:04:47 +01:00
Lars-Peter Clausen 81a17121b0 axi_dmac: Use internal enable signal for the request generator
All components should use the internal 'do_enable' signal instead of the
external 'enable' signal. The former correctly incorporates the shutdown
sequence and does not get asserted again until the shutdown has been
completed. Using the external signal can cause problems when it is disabled
and enabled again in close proximity.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:04:47 +01:00
Lars-Peter Clausen 23eb0d2428 axi_dmac: request_generator: Stop generating requests when disabled
Currently when the DMAC gets disabled the request_generator will still
generate all remaining burst requests for the currently active transfer.
While these requests will be ignored by the source and destination component
this can still take a fair amount of time for long transfers.

So just stop generating burst requests once the DMAC is being disabled.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:04:47 +01:00
Lars-Peter Clausen e15f0cd2c6 dmac: fifo_inf: Handle overflow and underflow correctly
Refactor the fifo_inf modules to always correctly generate the underflow and
overflow status signals. Before it was possible that in some cases they
were not generated when they should have been.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:04:47 +01:00
Lars-Peter Clausen ea84e93e1d axi_dmac: Correctly handle shutdown for the request splitter
We need to make sure to not prematurely de-assert the s_valid signal for the
request splitter when disabling the DMAC. Otherwise it is possible that
under certain conditions the DMAC is disabled with a partially accepted
request and when it is enabled again it will continue in an inconsistent
state which can lead to transfer corruption or pipeline stalls.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:04:31 +01:00
Lars-Peter Clausen 96b2a6d49a axi_dmac: Use internal enable signal for the request generator
All components should use the internal 'do_enable' signal instead of the
external 'enable' signal. The former correctly incorporates the shutdown
sequence and does not get asserted again until the shutdown has been
completed. Using the external signal can cause problems when it is disabled
and enabled again in close proximity.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:04:31 +01:00
Lars-Peter Clausen 4a69569265 axi_dmac: request_generator: Stop generating requests when disabled
Currently when the DMAC gets disabled the request_generator will still
generate all remaining burst requests for the currently active transfer.
While these requests will be ignored by the source and destination component
this can still take a fair amount of time for long transfers.

So just stop generating burst requests once the DMAC is being disabled.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:04:31 +01:00
Lars-Peter Clausen 6711390c01 dmac: fifo_inf: Handle overflow and underflow correctly
Refactor the fifo_inf modules to always correctly generate the underflow and
overflow status signals. Before it was possible that in some cases they
were not generated when they should have been.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:04:31 +01:00
Rejeesh Kutty 8839c8b18c xfer-logic: stretch toggles to allow capture 2015-02-06 22:07:00 -05:00
Rejeesh Kutty 8050a14bd8 xfer-logic: stretch toggles to allow capture 2015-02-06 22:06:56 -05:00
Istvan Csomortani 890bb1da75 daq2: Add support for VC707 2015-01-29 18:33:27 +02:00
Rejeesh Kutty 8fedb5b41c fifo2s: qualify last with valid 2015-01-15 09:34:43 -05:00
Adrian Costina 623e732ee6 kc705: Updated base project with linear flash. Updated all depending projects 2015-01-13 10:07:51 +02:00
Rejeesh Kutty 117686f352 ad9739a: updates for ad9739a 2015-01-09 10:54:50 -05:00
Rejeesh Kutty 785d3a4ae3 ad9739a: updates for ad9739a 2015-01-09 10:54:40 -05:00
Rejeesh Kutty e8d0782a2e ad9739a: updates for ad9739a 2015-01-09 10:54:22 -05:00
Rejeesh Kutty baea2090d6 ad9739a: updates for ad9739a 2015-01-09 10:54:12 -05:00
Rejeesh Kutty c9b6411e86 ad9739a: updates for ad9739a 2015-01-09 10:54:00 -05:00
Rejeesh Kutty a9cc8f6c91 ad9739a_fmc: added 2015-01-08 10:35:59 -05:00
Rejeesh Kutty 63633a0fa5 ad9739a: constraints 2015-01-08 10:25:45 -05:00
Rejeesh Kutty ed73a9d1cf ad9739a: updated to ad9739a 2015-01-08 10:25:15 -05:00
Rejeesh Kutty ad4b4f64d0 ad9739a: ad9122 copy 2015-01-07 15:36:02 -05:00
Rejeesh Kutty b65bcab8d6 up_clkgen: reading typo 2015-01-07 13:58:43 -05:00