Commit Graph

930 Commits (1c3795ad0278894ed5e253557eb4621ff5005069)

Author SHA1 Message Date
Istvan Csomortani 4cc69c0cac axi_ad9684: Add Makefile 2016-01-19 18:32:11 +02:00
István Csomortáni c865dbf353 axi_ad9680: Fix channel instantiation 2016-01-19 12:49:45 +02:00
István Csomortáni df3eefdca1 axi_ad9434: Update constraint file 2016-01-19 12:43:05 +02:00
Istvan Csomortani d1e638349b ad_serdes_clk : The reference clock selection line should by tied to 1
Just the CLKIN1 is used in the MMCM.
2016-01-19 11:18:00 +02:00
Istvan Csomortani c6cfd1a2b6 axi_ad9684: Initial check in 2016-01-19 11:13:45 +02:00
István Csomortáni 4f2b999999 axi_ad9680: Q_OR_I_N is not used in this channel 2016-01-13 16:26:22 +02:00
István Csomortáni 838b558176 axi_ad9434: Fix adc_status
adc_status was not driven by anything. Should be driven by adc_status_m1.
2016-01-13 12:21:42 +02:00
István Csomortáni 2dcd9136aa axi_ad6676: Delete confusing comment 2016-01-13 10:20:18 +02:00
Rejeesh Kutty 4c2d08a9be ad9152: altera syntax error 2015-12-11 12:49:00 -05:00
Rejeesh Kutty bc93910ee5 ad9152: qsys updates 2015-12-10 16:04:10 -05:00
Rejeesh Kutty ff1d98a0c7 ad9144: duplicate include 2015-12-10 16:02:35 -05:00
Rejeesh Kutty ce906989d5 ad9152: qsys ip 2015-12-10 09:46:31 -05:00
Istvan Csomortani 12c95b059d ad_tdd_control: Remove tdd_enable_synced control line
For a better timing and control, the valid control lines are gated with flops, instead of combinatorial logic.
This is the main reason why we do not need the tdd_enable_synced signal anymore. The out coming data is delayed by one clock cycle to keep data and control lines synced.
2015-12-03 11:16:28 +02:00
Adrian Costina 5cf45b2978 axi_clkgen: Added phase related parameters 2015-12-02 18:50:23 +02:00
Istvan Csomortani 36febf8591 Merge branch 'master' into dev
Conflicts:
	library/axi_ad9361/axi_ad9361_ip.tcl
	library/axi_dmac/Makefile
	library/axi_dmac/axi_dmac_constr.ttcl
	library/axi_dmac/axi_dmac_ip.tcl
	library/common/ad_tdd_control.v
	projects/daq2/common/daq2_bd.tcl
	projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
	projects/fmcomms2/zc706pr/system_project.tcl
	projects/fmcomms2/zc706pr/system_top.v
	projects/usdrx1/common/usdrx1_bd.tcl

This merge was made, to recover any forgotten fixes from master,
before creating the new release branch. All conflicts were reviewed
and resolved.
2015-11-26 13:38:11 +02:00
Adrian Costina 667e49fe41 library: Axi_clkgen, added register for controlling the source clock.
Address is 0x11 /0x44.
With the default value, 0, clock 1 is selected. If set to 1, clock 2 is selected
2015-11-25 11:16:32 +02:00
Adrian Costina df58646925 util_adcfifo: Updated altera interface 2015-11-25 10:20:06 +02:00
Istvan Csomortani 593c486168 ad_tdd_control: The state machine goes from OFF to ON, when a valid sync is received 2015-11-24 15:15:53 +02:00
Istvan Csomortani c70be7391f ad_tdd_control: Avoid unnecessary reset on control lines
No need to reset for tdd_last_burst, it's value depends on the tdd_burst_counter.
2015-11-24 15:13:18 +02:00
Adrian Costina ee0617661e axi_ad9680: Updated altera interfaces, added FIFO conduits per channel 2015-11-24 11:45:12 +02:00
Adrian Costina f51871c1e4 axi_ad9144: Updated altera interfaces, added FIFO conduits per channel 2015-11-24 11:44:07 +02:00
Adrian Costina 76823f95fa axi_ad9250: Updated altera interfaces, added FIFO conduits per channel 2015-11-24 11:39:55 +02:00
Adrian Costina 275ec3d3a8 axi_ad9361: Updated altera interfaces, added FIFO conduits per channel 2015-11-24 11:21:08 +02:00
Adrian Costina 250f3c917b axi_ad9361: Removed old signals from the altera device interface module 2015-11-24 11:20:35 +02:00
Adrian Costina fb269f7a29 util_cpack: Updated altera interfaces
- DMA side, simplified naming
- ADC side, added FIFO conduit per channel
2015-11-24 11:18:18 +02:00
Adrian Costina e6de2ade78 util_upack: Updated altera interfaces
- DMA side, simplified naming
- DAC side, added FIFO conduit per channel
2015-11-24 11:17:02 +02:00
Adrian Costina c5ff1674c6 axi_dmac: Updated fifo interfaces for easier connectivity 2015-11-24 11:08:28 +02:00
Adrian Costina e5d2f5be06 util_upack: Cosmetic changes 2015-11-24 10:55:10 +02:00
Adrian Costina 985f2ca020 library: ad_rst, added comment so that the registers are not minimized away 2015-11-24 10:33:38 +02:00
Istvan Csomortani bdf9754971 util_tdd_sync: Sync signals output reg is a false path source 2015-11-17 09:42:05 +02:00
Istvan Csomortani 9ba8c059ce ad_tdd_sync: Fix reset value of the pulse_counter 2015-11-13 18:31:24 +02:00
Adrian Costina 3c27b3a4c5 ad_lvds_in: Add single ended option 2015-11-13 12:13:09 +02:00
Istvan Csomortani b17fec689e ad_tdd_control: An active sync pulse can NOT be a reset for the control lines
By reset the control lines (RF, VCO and DP) on an active sync pulse, can cause glitches on the ENABLE/TXNRX lines. The sync pulse resets just the TDD counter.
2015-11-11 11:13:33 +02:00
Istvan Csomortani fc0f4bc414 axi_ad9361: Delete the old sync generator from the core
+ Define two control signal for util_tdd_sync : tdd_sync_en and tdd_terminal_type
+ Delete to old ad_tdd_sync.v instances from the core
+ Update Make files
+ Update ad_tdd_control: add additional CDC logic for tdd_sync (the sync comes from another clock domain)
+ Update the ad_tdd_sync module: it's just a simple pulse generator, the pulse period is defined using a parameter, pulse width is fixed: 128 x clock cycle
+ Update TDD regmap: tdd sync period is no longer software defined
2015-11-11 11:06:19 +02:00
Istvan Csomortani a290611c09 util_tdd_sync: Initial commit
A synchronization signal generator for AD9361 running on TDD mode.
If the associated device is master, the module generates a pulse in a defined interval. Otherwise receives the sync signal from outside.
2015-11-11 10:46:11 +02:00
Adrian Costina 5cc97c78d3 Makefiles: Update makefiles to include the nerw axi_gpreg / util_mfifo libraries 2015-11-10 09:32:50 +02:00
Adrian Costina e7fd964874 axi_clkgen: Added a second input clock option 2015-11-06 17:55:29 +02:00
Rejeesh Kutty 839e76996f axi_gpreg: added constraints 2015-11-05 11:28:37 -05:00
Rejeesh Kutty 482b740229 axi_gpreg: add buffer enable 2015-11-05 11:28:35 -05:00
Rejeesh Kutty 66d4f8fd58 util_gtlb: output receive/transmit clocks 2015-11-05 11:28:34 -05:00
Rejeesh Kutty 28bfeb442c util_gtlb- syntax error fixes 2015-11-05 11:28:31 -05:00
Adrian Costina 6d28a92b5b util_adcfifo: Added altera initial constraints file 2015-11-04 13:34:52 +02:00
Adrian Costina e8b84b3662 axi_dmac: Updated axis destination / source ports for altera component 2015-11-04 13:33:41 +02:00
Adrian Costina de53a61902 util_adcfifo: Put a limit on the read/write address from memory so there is no overflow
Added altera component
2015-11-04 13:31:50 +02:00
Adrian Costina 6cfc13a9dd common: Allow for the memory to be also symetrical 2015-11-04 13:28:02 +02:00
Rejeesh Kutty ad1cef1441 axi_gpreg: compile fixes 2015-11-03 14:29:00 -05:00
Rejeesh Kutty c8019b69fd axi_gpreg- added 2015-11-03 14:28:59 -05:00
Rejeesh Kutty 88f247a1de util_gtlb: use gpio 2015-11-03 14:28:57 -05:00
Lars-Peter Clausen acd9efc528 axi_hdmi_tx: Add parameter to configure the output clock polarity
In order to maximize the window where it is safe to capture data we ideally
want to launch data on the opposite edge to which it is captured. Since the
edge on which data is captured depends on the connected device add a
parameter that allows to configure the launching edge.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-11-03 10:59:13 +01:00
Rejeesh Kutty 88568c21e1 util_gtlb: updates for latest axi_jesd_gt 2015-10-30 18:47:36 -04:00