f3ffd5a63f
up_gt: separate pll resets to tx/rx
2015-10-02 13:58:30 -04:00
a679251d7d
Makefiles: Update Make
2015-09-09 17:13:19 +03:00
9bef9742b7
jesd_gt- cosmetic changes
2015-09-03 16:16:24 -04:00
18f688514b
2015.2 updates
2015-08-26 11:33:37 -04:00
7b858bc5ad
Revert commit 6b99ce
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Revert 6b99ce2482
2015-08-26 13:48:28 +03:00
6b99ce2482
library: Added common constraints for all cores. Commented code that needs to be updated to 2015.2
2015-08-20 18:17:38 +03:00
57cfb7cfb1
hdl/library: Update the IP parameters
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The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
c22d1c044b
axi_jesd_gt-- gt interfaces
2015-08-14 15:34:49 -04:00
a6f6c81795
axi_jesd_gt- gt lane split
2015-08-13 13:03:51 -04:00
3615c9cad7
axi_jesd_gt- bug fixes
2015-08-13 13:03:51 -04:00
8697b0a8d6
axi_jesd_gt- ip script changes
2015-08-13 13:03:51 -04:00
10d4da64dd
axi_jesd_gt: move master/slave control to a util module
2015-08-13 13:03:51 -04:00
3ed350efbc
axi_jesd_gt- split up
2015-08-13 13:03:51 -04:00
46fa91d5be
Makefile: Update Make files
2015-07-03 18:08:57 +03:00
6862655b0d
Add .gitattributes file
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Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
28e8275a5d
library/axi_jesd_gt: split gt lanes
2015-06-12 15:56:03 -04:00
04eb998ff1
axi_jesd_gt: constraints
2015-06-10 14:29:06 -04:00
e2f4a4c5cf
library: make preset registered for timing paths
2015-06-10 13:41:41 -04:00
df0eaad1e2
gt: constraints
2015-06-10 11:38:15 -04:00
c6ebab7393
library- drp moved to up clock
2015-06-01 13:39:26 -04:00
9762c65868
library- jesd-align port name change
2015-05-20 14:25:21 -04:00
e918588a4b
library: remove axi-min-size parameter
2015-05-19 13:07:48 -04:00
d623f77453
axi_jesd_gt: Added rx_jesd_rst and tx_jesd_rst.
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Resets for both up clock domain and rx clock domain are needed in some projects
2015-04-30 12:07:36 +03:00
a7a2d194e9
axi_jesd_gt: Switched rx_rst and rx_rst_done to up clock domain, to be compatible with xilinx JESD core
2015-04-28 15:04:18 +03:00
d42c0bc431
axi_jesd_gt : Added CDC and reset constraints
2015-04-23 11:03:51 +03:00
dc2b37bd0c
Makefile: Added top level Makefile. Modified behavior of clean and clean-all
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Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.
The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
374f82e7de
makefiles: The clean command for library won't remove the xml files, except for component.xml.
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Updated also the dmac dependencies
2015-04-16 11:53:27 +03:00
5f8e9a74ea
makefile: updated
2015-04-07 16:32:01 -04:00
f79a152958
Makefiles: updated all makefiles adding clean functionality
2015-04-03 11:57:54 +03:00
a63d4ae65c
makefile: added
2015-04-01 16:27:59 -04:00
9cdec38532
gt- report device type
2015-02-17 11:43:57 -05:00
fccadcec31
jesd_gt: lpm/dfe programmable
2015-02-13 11:33:25 -05:00
fd305f2eff
es: added kcu105 gth
2014-11-17 09:55:09 -05:00
f8e7796592
axi_jesd_gt: Fix lane number parameters
2014-11-12 17:43:32 +02:00
64ec633438
gt: asymmetric no of lanes
2014-11-11 08:54:24 -05:00
b11d80ed98
ad_rst: changed to dual stage
2014-11-05 16:48:02 -05:00
6f723ef9e5
axi_jesd_gt: lane mux on char qualifiers
2014-10-22 15:29:25 -04:00
9d43a08865
gt: constraint modifications
2014-10-15 14:51:01 -04:00
86724f7fc7
gt: tx lane interleaving
2014-10-15 14:51:00 -04:00
88a3b7f8fd
library: remove all constraints for now
2014-10-07 16:59:19 -04:00
de33722470
up/constr: independent read/write and local constraints
2014-10-02 14:35:59 -04:00
5af2474d51
usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization
2014-09-23 22:44:33 -04:00
41cc92ef49
Remove BASEADDR/HIGHADDR parameters
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This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
b481df0b5f
library: local constraints async groups
2014-08-14 15:09:51 -04:00
01963b01fc
jesd_gt: local constraints
2014-08-14 15:09:49 -04:00
cf56a568c6
kcu105: GTH updates
2014-06-05 14:27:38 -04:00
916afd460f
axi_jesd_gt: synchronization support
2014-05-19 14:17:31 -04:00
80e5051894
axi_jesd_gt: initial checkin
2014-04-01 15:14:28 -04:00
Rejeesh Kutty
Istvan Csomortani
Adrian Costina
Lars-Peter Clausen