Commit Graph

21 Commits (1d4b92190aab3ed96cbde543a14ca162f7b14fb5)

Author SHA1 Message Date
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Istvan Csomortani c1bdfca4c3 library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
Rejeesh Kutty 8063ba2b66 make updates 2017-03-20 16:05:18 -04:00
Istvan Csomortani 7478777d8d axi_dacfifo: Match the ports with util_dacfifo 2017-03-03 18:46:16 +02:00
Rejeesh Kutty 3586397f57 altera/common- add asymmetric fifo 2017-03-01 15:35:04 -05:00
Rejeesh Kutty 104e9dfcdc adc/dac-fifo altera cores 2017-02-28 13:30:50 -05:00
Istvan Csomortani 11623e79be axi_dacfifo: Fix clock for read address generation 2017-02-24 15:47:04 +02:00
Istvan Csomortani 3e596347fd axi_dacfifo: Delete unused wires 2017-02-24 15:45:51 +02:00
Istvan Csomortani ac2e5a9dac constraints: Update constraints
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
Istvan Csomortani f326c03ff3 axi_dacfifo: Define constraint for bypass
The bypass module currently is supported, when the DMA data width
is equal with the DAC data width.
The dac_data output is enabled with dac_valid.
2017-02-24 12:35:42 +02:00
Istvan Csomortani b9d3039568 axi_dacfifo: Register the dac_valid signals 2017-02-24 12:34:58 +02:00
Istvan Csomortani debc6e2066 axi_dacfifo: Data from DMA is validated with dma_ready too 2017-02-24 12:32:25 +02:00
Istvan Csomortani dfcd5214a0 axi_dacfifo: axi_dvalid should come from dacfifo_rd module 2017-02-24 12:28:46 +02:00
Istvan Csomortani 1fce57f6c3 axi_dacfifo: Redesign the bypass functionality 2017-02-23 17:32:31 +02:00
Istvan Csomortani e3ac341aad axi_dacfifo: Fix constraints 2017-02-21 14:45:18 +02:00
Istvan Csomortani 981a61bf16 axi_dacfifo: Clean up the axi_dacfifo_wr.v module 2017-02-17 18:40:02 +02:00
Istvan Csomortani f10866e4c3 axi_*fifo: Delete/replace AXI_BYTE_WIDTH parameter 2017-02-16 19:54:41 +02:00
Istvan Csomortani 95a4ea20c8 axi_dacfifo: Delete redundant parameter BYPASS_EN 2017-02-16 19:53:44 +02:00
Adrian Costina 8ebc8fe4e2 updated makefiles 2016-12-09 23:06:41 +02:00
Rejeesh Kutty 9defccef70 dacfifo- axi address map fixes 2016-09-27 14:48:23 -04:00
Istvan Csomortani 3b0c1e02fc axi_dacfifo: Move IP to library/xilinx 2016-09-15 11:38:16 +03:00