Commit Graph

10 Commits (1e31b9dd97b6534ff678cac9157bcf83748c640e)

Author SHA1 Message Date
Adrian Costina c4b94fc564 adrv9009zu11eg: Add S JESD204 parameter for the projects 2020-02-18 11:19:02 +02:00
Adrian Costina 645696e5b4 adrv9009zu11eg: Extend SPI connection to the PL HD PINS expansion 2020-02-18 11:19:02 +02:00
Adrian Costina d2817863a1 adrv9009zu11eg: Add FMCOMMS8 support 2020-02-18 11:19:02 +02:00
Adrian Costina 29f18e501e adrv9009zu11eg: Cleanup bd file 2020-02-18 11:19:02 +02:00
Arpadi 74fc68d4c3 axi_fan_control: Changed temperature thresholds to registers
implemented mux for temp reading either from internal or external
source; updated regmap; added param to identify source for temp
information; updated tacho measurements; added AVG_POW param used
for tacho measuremet average useful for simulations; defaults for
tacho measurements changed to params and added registers; added
prescaler for fsm control, FSM updated; changed register write
process; connected INTERNAL_SYSMONE to regmap, value can now be
read by software;
2020-02-14 11:21:12 +02:00
Adrian Costina 09ad67bfd7 adrv9009zu11eg: Make the project more parametrizable 2019-12-04 14:59:18 +02:00
Adrian Costina 0cb5c0bdaf adv9009zu11eg: Update FPGA to -2. Update DDR4 clock frequency 2019-11-27 16:27:44 +02:00
Adrian Costina dfe3258a4f adrv9009zu11eg: Add axi_sysid 2019-11-19 10:29:57 +02:00
Adrian Costina 81d3a9eb66 adrv9009zu11eg: Reduce SPI Clock speed to meet timing 2019-11-19 10:29:57 +02:00
Adrian Costina a589a2c7eb adrv9009_zu11eg_som: Change design partitioning
Create a structure similar with ADRV936x projects
2019-11-14 15:25:23 +02:00