AndreiGrozav
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e736504e0f
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fmcjesdadc1, usdrx1: Using the same clock in rx_data path
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2017-03-10 14:26:51 +02:00 |
Rejeesh Kutty
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aa6c94c993
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usdrx1/a5gt: ddr3 use ip constraints
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2016-12-22 14:14:21 -05:00 |
Istvan Csomortani
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f47863bbcf
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usdrx1: Integrate ad_syref_gen into the project
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2016-12-19 14:36:01 +00:00 |
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Rejeesh Kutty
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f799c40cf0
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usdrx1/a5gt- xcvr interface changes
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2016-12-08 16:05:23 -05:00 |
Adrian Costina
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2dfcb0c599
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usdrx1: Initial commit for a5gt
axi_ad9671: added start of frame information to the altera core.
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2014-10-07 19:41:54 +03:00 |