21208ca208
Makefiles: Update Makefiles
2016-03-31 12:37:47 +03:00
657144d9a7
a10gx: Updated base design and DAQ2 to the new revision of the a10gx board
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- tried using ATX PLL and fPLL for TX transceiver clocks, but could not get them to lock
- CMU PLL works correctly as temporary solution
2016-03-28 13:21:36 +03:00
7c2f34549b
motcon2_fmc: Update common design to 2015.4
2016-03-23 10:27:07 +02:00
b31cdac6bd
util_gmii_to_rgmii: Updated to 2015.4
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The Xilinx interface changed its name from gmii_rtl_1 to gmii_rt_1
2016-03-23 10:14:18 +02:00
769fecbe00
axi_i2s_adi: Fixed clock association
2016-03-21 20:18:45 +02:00
714caa964c
usdrx1: Update common design to 2015.4
2016-03-18 16:29:43 +02:00
05f4f3ac09
usb_fx3: Update common design to 2015.4
2016-03-18 16:16:38 +02:00
24fdd2b9b7
pzsdr/ccpci: Update common design to 2015.4
2016-03-18 15:30:10 +02:00
f8b155faab
pzsdr/ccfmc: Update common design to 2015.4
2016-03-18 15:28:56 +02:00
d567af54ef
imageon: Update common design to 2015.4
2016-03-18 15:27:31 +02:00
995debedce
fmcomms2: Update common design to 2015.4
2016-03-18 15:26:52 +02:00
b555be25d5
kcu105: Update common design to 2015.4
2016-03-18 15:22:42 +02:00
412013d939
adv7511: Update common design to 2015.4
2016-03-18 15:01:25 +02:00
6d277733d5
axi_spdif_rx: Fixed the clock association
2016-03-18 13:58:13 +02:00
28990e362a
axi_spdif_tx: Fixed the clock association
2016-03-18 13:31:06 +02:00
d355aa0ea6
daq3/zc706: Updated design to 2015.4
2016-03-17 11:46:48 +02:00
012b095006
daq3: Updated common design to 2015.4
2016-03-17 11:44:27 +02:00
38c3f7474a
ad6676: Updated common design to 2015.4
2016-03-17 11:40:46 +02:00
abc03fff2c
fmcomms7: Updated design to 2015.4
2016-03-17 09:11:41 +02:00
59c726ecbe
fmcjesdadc1: Updated common design to 2015.4
2016-03-16 10:14:06 +02:00
1a3aab0c13
fmcomms1: Updated common design to 2015.4
2016-03-16 10:09:54 +02:00
b7be089b82
daq2: Updated common design to 2015.4
2016-03-16 10:02:42 +02:00
334fce03a3
fmcadc4/zc706: Updated design to 2015.4
2016-03-15 15:28:11 +02:00
e8dd5f9788
fmcadc4: Updated common design to 2015.4
2016-03-15 15:27:25 +02:00
98cc7dad7d
fmcadc2: Updated common design to 2015.4
2016-03-15 15:26:05 +02:00
ceea7f25b2
fmcomms2: Updated common design to 2015.4
2016-03-15 15:23:20 +02:00
6f03998b95
zc702: Updated common design to 2015.4
2016-03-15 15:21:22 +02:00
a0c5f46940
zed: Updated common design to 2015.4
2016-03-15 15:20:46 +02:00
9a258d5e4c
vc707: Updated common design to 2015.4
2016-03-15 15:20:02 +02:00
bcf5bd8137
mitx045: Updated common design to 2015.4
2016-03-15 15:18:31 +02:00
27f5f1dcbe
kc705: Updated common design to 2015.4
2016-03-15 15:17:53 +02:00
eb743e0e03
ac701: Updated common design to 2015.4
2016-03-15 15:17:02 +02:00
d282064103
zc706: Updated common design to 2015.4
2016-03-15 15:16:36 +02:00
71be9519ec
adi_project.tcl: Updated to 2015.4
2016-03-15 15:03:50 +02:00
9b2a106aa0
axi_jesd_gt: changed clock and reset naming to be consistent with the other projects
2016-03-15 11:20:31 +02:00
06b7916303
axi_spdif_tx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred
2016-03-15 10:18:25 +02:00
ef05642e26
axi_spdif_rx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred
2016-03-15 10:14:05 +02:00
b3ed38107c
axi_i2s_adi: changed adi_ip_properties lite to adi_ip_properties, so that the axi interface can be inferred
2016-03-15 10:12:45 +02:00
31cc91d1b9
adi_ip: Updated to 2014.4.2
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- automatically infer clocks, resets, axim_mm and axis interfaces
2016-03-14 15:14:18 +02:00
2524f19ae0
Updated interfaces Makefile and Makefiles for the libraries that depend on it
2016-03-07 12:31:41 +02:00
40fb68dfd5
ad9265, ad9434, ad9467, daq1, daq2, daq3, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1, fmcomms6, fmcomms7, usdrx1: updated common spi module so that spi streaming is possible
2016-03-02 13:39:37 +02:00
becc23a69b
daq2: Modified common spi module so that spi streaming is possible
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- stop incrementing spi_count after the instruction cycle
2016-03-01 17:25:58 +02:00
f6e64e42b0
kcu105: add ethernet idelaycntrl
2016-02-26 13:19:49 -05:00
8ccd8d87bb
daq2: A10GX, increase analog/digital reset durations
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- reset the xcvr_rst_cntrl only from the axi_jesd_xcvr
- checked separate RX/TX reset per channel
2016-02-23 11:41:38 +02:00
89f7aadfb1
fmcjesdadc1: A5GT, connected xcvr_rxt_cntrl reset input to the axi_jesd_xcvr reset output
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This will allow for the transceivers to be reset by the axi_jesd_xcvr core
2016-02-23 11:31:07 +02:00
0f37dd6424
fmcjesdadc1: Fixed project
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- changed system_project.tcl so that all base designs to be included
- changed DMA properties to take into consideration the new parameter names
- changed reset bridges to asynchronous
- increased maximum burst size of the DMA bridge
- changed the data_width of the memory bus to 256, as with 512 timing violations may occur
- changed base addresses for the base system to be the same as in the previous release
2016-02-19 14:09:57 +02:00
d94f157454
arradio: Changed ADC/DAC DMA address length to 24 bit
2016-02-16 15:27:51 +02:00
43e03ca6f7
arradio: Updated project
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- made the reset bridges asynchronous
- connected the arradio gpio to the CPU interconnect
2016-02-16 14:50:23 +02:00
61f9f72a75
fmcjesdadc1: Updated VC707 project for maximum throughput from DMA to DDR
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- Increased the DMAs internal FIFO
2016-02-09 12:30:56 +02:00
c431adb793
fmcjesdadc1: Updated KC705 project for maximum throughput from DMA to DDR
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- Increased the DMA internal FIFO
2016-02-09 12:00:27 +02:00
AndreiGrozav
Adrian Costina
Rejeesh Kutty