1cd3435147
up_delay_cntrl- cosmetics
2015-08-28 13:16:18 -04:00
8fddf983d2
up_hdmi_tx- common/generic instance names
2015-08-27 13:17:06 -04:00
20ee10ea46
common/ad_lvds_out- add single ended
2015-08-27 11:41:47 -04:00
ba64de228e
ip-constr- register name changes
2015-08-27 11:18:00 -04:00
0077117f94
dac/adc- make common instances
2015-08-21 14:41:39 -04:00
c45d39df51
dac/adc- make common instances
2015-08-21 14:41:35 -04:00
e3ec6b48fc
dac/adc- make common instances
2015-08-21 14:41:30 -04:00
f31c1c9caa
dac/adc- make common instances
2015-08-21 14:41:26 -04:00
e4e4700950
dac/adc- make common instances
2015-08-21 14:41:13 -04:00
54b4365f6c
dac/adc- make common instances
2015-08-21 14:41:09 -04:00
799001403f
mult-macro: use primitive parameters
2015-08-20 13:54:16 -04:00
b0079e60bf
ad-rst - common instance for adc/dac
2015-08-20 11:37:16 -04:00
6ae0c8f85e
library: Fixed changes related to parameters
2015-08-20 18:13:54 +03:00
928ee4972b
dac/adc-rst: common ad-rst instance
2015-08-19 14:54:43 -04:00
483e375910
dac/adc-rst: common ad-rst instance
2015-08-19 14:54:38 -04:00
f8b3346e97
axi_jesd_xcvr- ad_rst register changes
2015-08-19 13:26:38 -04:00
57cfb7cfb1
hdl/library: Update the IP parameters
...
The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
10d9de39a1
axi_ad9361/tdd: Update the synchronization logic
...
The master will regenerate a sync pulse periodically. The period can be defined by software.
2015-08-19 12:21:23 +03:00
041be729f6
common/ip-constrs- uniform simple constraints will do
2015-08-13 13:03:51 -04:00
a2b816beda
common/up_hdmi_tx: wrong clock on vdma status signals
2015-08-13 13:03:51 -04:00
5edf61c40a
ad_rst:- allow preset to be synchronized as reset
2015-08-13 13:03:51 -04:00
2bcac36e33
common/up_- change to asynchronous resets
2015-08-13 13:03:51 -04:00
10d4da64dd
axi_jesd_gt: move master/slave control to a util module
2015-08-13 13:03:51 -04:00
e4f94664a6
axi_jesd_gt- remove per lane control/status to channel
2015-08-13 13:03:51 -04:00
f807490ed1
axi_jesd_gt- per lane group
2015-08-13 13:03:51 -04:00
4c8206608c
axi_jesd_gt- separate es-axi
2015-08-13 13:03:51 -04:00
e4b0710923
axi_jesd_gt- per lane split-up
2015-08-13 13:03:51 -04:00
ad80561379
TDD_regmap: Fix CDC for control signals
2015-08-06 15:16:39 +03:00
e19d476b58
TDD_regmap: Fix addresses
2015-08-06 15:15:50 +03:00
d2c99acae8
fmcomms2/TDD: Update synchronization interface
...
Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 15:14:36 +03:00
8e631e56d6
fmcomms2: Add a synchronization interface for TDD mode.
...
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 14:42:54 +03:00
cd5ce3349f
iqcor- move i/q sel inside the module
2015-07-23 15:55:45 -04:00
a4461545fa
axi-ip: constraints - altera
2015-07-22 12:46:06 -04:00
559893c0a3
altera- obsolete cores
2015-07-21 11:04:26 -04:00
86dabbe5fc
jesd-align-- xilinx/altera merge
2015-07-21 10:57:00 -04:00
9f7fff2d2f
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic
...
Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 14:10:49 +03:00
6e3817d419
axi_jesd_xcvr: individual reset control
2015-07-13 10:04:34 -04:00
b25b2e3020
registers for signal tap
2015-07-08 15:47:45 -04:00
ea2bd71904
synchronize up signals separately
2015-07-07 12:51:13 -04:00
c1fcbeec8e
library/axi_jesd_xcvr: interface name matching
2015-07-07 10:21:53 -04:00
3a5da47239
xcvr- initial checkin
2015-07-06 13:51:55 -04:00
cf6052e2a8
axi_hdmi_tx: Add control to bypass chroma sub-sampler
...
Add a control bit to the register map that allows to bypass the chroma
sub-sampler in the axi_hdmi_tx core. This is primarily interned to be used
to send the test-pattern directly to the HDMI transmitter without modifying
it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 21:16:09 +02:00
d6c64e031f
axi_hdmi_rx: Drop TPG enable from register map
...
The TPG is no longer part of the RX core and the corresponding bit in the
register map isn't hooked up to anything. So drop it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
542d64bb5a
up_hdmi_rx: Fix enable control
...
Connect the enable signal in the register map to the up_preset signal so
that it is possible to enable/disable to core at runtime.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
231a21548c
up_hdmi_rx: Fix TPM OOS clear
...
The TPM OOS status flag is in bit 1. Make sure writing to bit 1 rather than
bit 0 clears the TPM OOS.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
185e489802
cpack- signaltap mess
2015-06-29 16:31:53 -04:00
6862655b0d
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
ac6e28c461
library/common: add altera signaltap
2015-06-19 14:33:01 -04:00
ddc08c960c
ad_tdd_control: Connect the reset to all the flops
2015-06-11 12:07:47 +03:00
e2f4a4c5cf
library: make preset registered for timing paths
2015-06-10 13:41:41 -04:00
Rejeesh Kutty
Adrian Costina
Istvan Csomortani
Lars-Peter Clausen