Adrian Costina
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fd3910a915
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fmcjesdadc1: Updated a5gt design
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2015-11-24 15:39:21 +02:00 |
Rejeesh Kutty
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3ccf1bef36
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base system modifications
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2015-07-23 15:23:10 -04:00 |
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Rejeesh Kutty
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a454b73d27
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fmcjesdadc1/a5gt: split xcvr cores
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2015-07-15 09:44:53 -04:00 |
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Rejeesh Kutty
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bbf1c5b803
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transceiver core added/gpio removed
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2015-07-07 15:30:38 -04:00 |
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Rejeesh Kutty
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330c205e8e
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fmcjesdadc1- sys_clk changes
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2015-06-30 10:47:21 -04:00 |
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Rejeesh Kutty
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543e08b67a
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fmcadc1: sdc updates
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2015-06-25 04:25:39 -04:00 |
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Rejeesh Kutty
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15740a7d34
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fmcjesdadc1- 15.0 updates
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2015-06-24 05:31:09 -04:00 |
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Rejeesh Kutty
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0a8823361f
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fmcjesdadc1/a5gt: 14.1 updates
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2015-04-03 14:54:57 -04:00 |
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Adrian Costina
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9672271155
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fmcjestadc1: a5gt: Updated project to work with linux and fixed ethernet
- added phy reset mechanism for proper functioning of the ethernet
- not all DDR is accesible, as NIOS2 can't access it with MMU enabled
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2015-01-23 13:30:56 +02:00 |
Lars-Peter Clausen
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50faf0c53a
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Remove executable flags from non-exectuable files
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2014-09-09 15:05:06 +02:00 |
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Rejeesh Kutty
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cb29b83b05
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a5gt: updates to match a5gt
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2014-08-25 10:46:59 -04:00 |
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Rejeesh Kutty
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6a19b34a00
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a5gt: added tightly coupled memory
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2014-04-03 20:50:17 -04:00 |
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Rejeesh Kutty
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12e5cc91bd
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make signaltap/timing part of the flow
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2014-04-03 20:50:15 -04:00 |
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Rejeesh Kutty
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e85153b5dd
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altera hal version
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2014-04-01 21:12:11 -04:00 |
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Rejeesh Kutty
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04df908fbf
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altera-fmcjesdadc1 initial checkin
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2014-04-01 12:01:57 -04:00 |
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Rejeesh Kutty
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0d678b89ed
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altera a5gt fmcjesdadc1 setup
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2014-04-01 11:46:37 -04:00 |