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7 Commits (219680968e8a120c8242eac17bed00698c477f19)

Author SHA1 Message Date
Iulia Moldovan c9a7d4d927 Add copyright and license to .tcl, .ttcl files 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-07-25 15:22:26 +03:00
laurent-19 2ae09c9808 Check guidelines. Remove redundancies 
* Removed empty/commented lines
 * Regenerated Makefiles
 * Removed redundancies adc channels data width
 * Set data width 32-bit: max resolution and CRC header

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 2023-03-29 15:08:07 +03:00
Sergiu Arpadi 445cca61ef SPI Engine: Update spi_engine.tcl 
The SPI Engine cores were named directly inside the script and this
would mean that for multiple SPI Engine instances IPs with the same
name would appear. These updates will introduce the hierarchy name
into the name given to the cores and will therefore allow for
multiple instances of SPI Engine to be added to the same Xilinx
project.

Projects which use spi_engine.tcl will be updated to account for
these changes.
 2023-03-29 15:08:07 +03:00
Sergiu Arpadi f64830364c ad469x: Use axi_pwm_gen; clean-up 
Replace axi_pulse_gen with axi_pmw_gen for softare support
considerations. Remove common/config.tcl and update project scripts
accordingly.
 2022-11-18 12:54:45 +02:00
sergiu arpadi 5359d991b2 ad469x_zed: Update bd.tcl with new port names 2020-10-28 11:31:50 +02:00
Istvan Csomortani ad4adddbe5 ad469x_fmc: Minor cosmetic update on the config file 2020-10-27 10:09:50 +02:00
sergiu arpadi 35e4eb6a7b ad469x: Add reference design for ad469x eval board 2020-10-22 19:17:10 +03:00