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25 Commits (219680968e8a120c8242eac17bed00698c477f19)

Author SHA1 Message Date
Iulia Moldovan c9a7d4d927 Add copyright and license to .tcl, .ttcl files 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-07-25 15:22:26 +03:00
Iulia Moldovan 1cac2d82e1 Add copyright and license to .xdc files 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-07-25 11:03:02 +03:00
Iulia Moldovan 28c06d505f Add/edit copyright and license for .v, .sv files 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-07-11 15:17:41 +03:00
Bogdan Luncan e1af7837da ad9081: Parameters and header update 
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
 2023-05-10 12:59:58 +03:00
Bogdan Luncan 73af87a324 ad9081: Versal transceiver update 
- Remove 4 lane limitation
- Adds support for RX or TX only instantiation

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
 2023-05-10 12:59:58 +03:00
Iulia Moldovan db94628cc6 library & projects: Update Makefiles 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-01-27 11:54:05 +02:00
Ionut Podgoreanu 5b95b6ce1f ad9081_fmca_ebz: Integrate the new TDD in project 2022-12-13 16:26:02 +02:00
Bogdan Luncan 72313df81f Updated the makefiles to build the projects in subdirectories based on the build parameters. 
Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.

Note that the 'JESD' and 'LANE' words from the parameter names are stripped.

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
 2022-11-14 09:38:42 +02:00
LIacob106 158c10df34 projects: starndadize the jesd make parameters 2022-09-13 11:53:21 +03:00
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file 
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
 2022-08-08 13:52:54 +03:00
Laszlo Nagy 2b274f945f ad9081_fmca_ebz: Reset cpack with Rx data offload 2022-08-01 12:47:26 +03:00
Iulia Moldovan 961ebe0cc2 projects: Update .v files according to guideline 
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
 2022-06-28 18:06:56 +03:00
Laszlo Nagy b3d231e569 ad9081_fmca_ebz/zc706: Make second sync CMOS and GPIO controllable 2022-05-26 09:13:05 +03:00
Laszlo Nagy 97b92565b2 Makefile: Replace util_fifo2axi_bridge with util_hbm 2022-04-28 14:31:32 +03:00
Dan Hotoleanu 77f3e5155b ad9081_fmca_ebz: Fix signal length parameter 
Corrected the length parameter for the rx_data input.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
 2021-12-08 14:29:48 +02:00
Filip Gherman 9295218a64 projects/ad9081_fmca_ebz: Updated makefiles 2021-10-05 16:56:57 +03:00
Laszlo Nagy 51b643b978 Makefile: Fix misc makefiles from projects and library 2021-10-05 14:24:48 +03:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
David Winter e9e278c898 ad9081_fmca_ebz: Remove bypass gpio 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
Laszlo Nagy 0d9e38bdbe ad9081_fmca_ebz: Update path to common block design 
Use absolute paths so ad9082 wrapper project can include the
system_bd.tcl instead of duplicating code.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy 680d28476c ad9081_fmca_ebz: Add LANE_RATE param to all projects 
The block design expects a lane rate to be set in the system project.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy d0f8a81b2f ad9081_fmca_ebz: Np 12 support 
204B functional
204C functional
 2021-02-05 15:24:15 +02:00
Sergiu Arpadi 6f2f2b8626 makefile: Regenerate make files 2021-01-20 01:02:56 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a 
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
 2021-01-20 01:02:56 +02:00
Laszlo Nagy ad755788a0 ad9081_fmca_ebz/zc706: Initial version 
M=8 L=4 SampleRate=250 MSPS
LaneRate=10 Gbps
 2020-11-12 15:46:27 +02:00