c9a7d4d927
Add copyright and license to .tcl, .ttcl files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 15:22:26 +03:00
1cac2d82e1
Add copyright and license to .xdc files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 11:03:02 +03:00
28c06d505f
Add/edit copyright and license for .v, .sv files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-11 15:17:41 +03:00
db94628cc6
library & projects: Update Makefiles
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-01-27 11:54:05 +02:00
1eb5f4985b
projects/common: Add build files templates carriers. Modified Quartus Versions
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The build files are available for the following carriers:
* intel: a10gx, a10soc, c5soc, de10nano, s10soc
* xilinx: coraz7s, kc705, kcu105, vc707, vc709,
vck190, vcu118, vcu128, vmk180,
zc702, zc706, zcu102, zed
* Added Makefiles, system_constr.sdc, system_qsys intel
* Added Makefiles, system_bd, system_constr xilinx
* de10nano, c5soc: Changed quartus version from 20.1.1 to 21.1.0
according to last commit update
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-10-05 10:47:21 +03:00
6b94259a52
projects/common: Add system_top _project templates
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Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
projects/common: Correct code and modify according to guidelines
* Added spacing to ports declaration
* Corrected coding mistakes/misspelling
* Modified/added variables names
* Added seetings (intel) and removed specific optimization settings
* Added assignments to unassigned pins (gpios)
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
projects/common: Correct/Add missing wrapper ports and iobufs
* Added port in wrapper (mainly spi) according to base design file
* Added instances of iobufs where missing
* Corrected gpio assignments or added missing ones
* Corrected minor guidelines mistakes
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
ac701/system_top.v: Change top based on previous projects
* Looked at fmcomms1, fmcomms2 from hdl_2016_r1 and datasheet
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
projects/common: Modify templates to build without errors
* Changed path for adi_env.tcl
* Moved adi_project command before assign intel
* Removed unnecessary spi signals
* Added spi ports with default logic
* a10soc: Removed pl-ddr signals and ports
* ac701: system_bd: Modified mdio interface
system_project: Added adi_board, adiobuf sourcing
system_top: Removed hdmi, i2c, fanpwm, spdif ports
according to base design
* c5soc: Added version settings
Removed unused gpios
* microzed: system_bd: Enabled RTS1 to use FCLK
system_top: Removed hdmi, i2c, unused gpios
* vc709: Separated input from ouput gpio, according to bd
Removed unnecessary ports
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
projects/common: Delete microzed vmk_es templates
* Removed hp0 interconnect from cora base design
* Added extra line to files de10nano
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-09-20 17:00:49 +03:00
72cf8f9b5d
projects/common: Add fmc connection files for every platform
2022-09-20 14:11:08 +03:00
b7f34f7bd9
adrv9009zu11eg & common/zcu102 : Fix zynqmp ref clock definition
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The derived clocks of the zynqmp core are not calculated correctly due
rounding issues, instead of 100MHz the value of 99999001 is received
causing warnings during system validation.
This can be fixed/worked around with the proper reference clock
definition.
2021-08-20 10:46:09 +03:00
0261eade0c
zynq:all: fix SPI clock constraint
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According to data sheets the EMIO SPI controller maximum frequency is
just 25MHz. Constrain the SPI clock accordingly.
2019-08-09 16:39:56 +03:00
0680e44330
system_id: deployed ip
2019-08-06 16:53:11 +03:00
de510b45ab
base: Add system_processor_rst for all the global clocks
2019-06-11 18:13:06 +03:00
20c714eccf
common: Define three global clock nets
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For all the Xilinx base design, define three global clock nets, which
are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk
and $sys_iodelay_clk.
These clock nets are connected to different clock sources depending of
the FPGA architecture used on the carrier. In general the following
frequencies are used:
- sys_cpu_clk - 100MHz
- sys_dma_clk - 200MHz or 250Mhz
- sys_iodelay_clk - 200MHz or 500Mhz
2019-06-11 18:13:06 +03:00
5986e87a1f
zynq/zynqmp: create a 50MHz clock on the SPI clock outputs of the PS
2019-05-30 14:55:11 +03:00
ebae8bf8c1
Remove interrupts from system_top for all xilinx projects
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- remove interrupts from system_top
- for all suported carriers:
- remove all interrupt bd pins
- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
2018-08-10 10:10:58 +03:00
bcba21da71
zcu102: updated IOSTANDARD of Bank 44 IOs to match VCCO 3.3V
2018-06-05 08:52:50 +01:00
b7ce81686a
common/zcu102: Fix ps8 ref clock 0 frequency assignament
2017-08-22 15:37:59 +03:00
41e247d426
common/zcu102: Add gpio_t connections
2017-08-22 15:37:59 +03:00
2d64d43475
ZCU102: SPI assign chip selects individually
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Otherwise, Vivado 2016.4 sets all of the CSNs equal to CSN0. This fix is needed to get the FMCOMMS5 working properly on the ZCU102 (#36 )
2017-07-21 09:22:10 +01:00
f3959cb5b9
zcu102- 2016.4 updates
2017-05-18 14:17:20 -04:00
f0bc3e20ef
zcu102: Automatic IP version update fix
2017-05-02 12:52:43 +03:00
cd8f4f23be
zcu102: Automatic IP version update
2017-05-02 12:30:00 +03:00
c39ed08edd
zcu102/*- actual clock == desired clock
2017-02-06 12:53:47 -05:00
721ee98a06
zcu102- misc fixes
2016-10-06 10:18:14 -04:00
baabe20766
common/zcu102- spi connections & clock
2016-10-05 14:01:59 -04:00
9afff7ae60
common/zcu102- 2016.2 updates
2016-09-30 11:55:10 -04:00
f3f5353944
zcu102- updates
2016-05-10 15:40:41 -04:00
e8fbdd0f5d
zcu102: zynq ultrascale
2016-05-10 15:40:41 -04:00
Iulia Moldovan
laurent-19
AndrDragomir
Laszlo Nagy
Arpadi
Istvan Csomortani
AndreiGrozav
Nick Pillitteri
Rejeesh Kutty