Some IPs like JESD link layer were marked as not supported on Versal devices by
the current flow while other not (e.g. TPL).
The auto family support seems to workaround this issue.
This commit fixes an issue in situations where we provide an oversized
transaction to the data offload in TX mode. Previously, the data offload
would stop accepting new data (wr_ready <= 0) after filling up the
internal storage, and get stuck waiting for the input transaction to
end, thus locking up the device.
This commit addresses that issue by allowing the data offload to consume
the full input transaction, even if the tail of the buffer will be
truncated in the output.
Signed-off-by: David Winter <david.winter@analog.com>
This commit adds a new synthesis option to the design, that controls
whether an internal clock domain crossing will be generated. Disabling
this option allows you to use a synchronization signal that is
synchronized to the write clock domain externally, and possibly shared
between multiple devices.
The default value retains the old behavior.
Signed-off-by: David Winter <david.winter@analog.com>
Add CMOS support for the interface for the following symbol modes on Xilinx devices:
A B C D E F G H
CSSI__1-lane 1 16/8 80(SDR)/160(DDR) 80 - SDR/DDR SDR/DDR->4/2(C=16), 2/1(C=8)
Columns description:
A - SSI Modes
B - Data Lanes Per Channel
C - Serialization factor Per data lane
D - Max data lane rate(MHz)
E - Max Clock rate (MHz)
F - Max Sample Rate for I/Q (MHz)
G - Data Type
H - DDS Rate
CSSI - CMOS Source Synchronous Interface
This commit changes the transfer length register to work in increments of
64 bytes and without offset. The true transfer length can now be
determined by multiplying the value of the transfer_length register with
64.
A value of zero is interpreted as a request for all available storage.
Additionally, this commit fixes an off by one issue that was discovered
during testing of the RX path.
Signed-off-by: David Winter <david.winter@analog.com>
Update vivado version to 2020.2:
- update default vivado version from 2020.1 to 2020.2
- add conditions to apply specific contraints only in Out Of Context mode.
- update DDR controler parameters for vcu118 and kcu105 dev boards
The width of the parameter `device_cfg_octets_per_multiframe` doesn't match the width in the submodules and corresponding slave module jesd204_tx, resulting in a warning generated during validation in Vivado. This patch increases the width of this parameter in axi_jesd204_tx.
Laszlo Nagy
Laszlo Nagy
David Winter
Filip Gherman
stefan.raus
Mihaita Nagy
AndreiGrozav
Adrian Costina
Robin Getz
Iacob_Liviu
alin724
Istvan Csomortani
Nick Pillitteri
Isaac T