The introduction of sysid IPs on some Stratix 10 projects introduced a
problem where they would fail to build, due to mem_init_sys_file_path
not being defined. This is fixed now.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
* Projects: Add missing sysid IP
* Added make parameters for the sysid ip for the projects: ad9209_fmca_ebz/vck190, ad9213_dual_ebz/s10soc and adrv9009/s10soc
Signed-off-by: Pop Ioan Daniel <pop.ioan-daniel@analog.com>
Add a list with make commands with the proper parameters for each devicetree
availible at the moment.
Signed-off-by: LIacob106 <liviu.iacob@analog.com>
Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.
Note that the 'JESD' and 'LANE' words from the parameter names are stripped.
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
In some cases (GTX2) the transceiver may gate the out_clk when it is in
reset or misconfigured. This will stop the clock generators from getting
a clock prior removing the reset of the XCVR. The XCVR has a requirement
of running user clock while removing the reset. The correct sequence must be :
Enable device clocks (user clock)
Remove the reset from the XCVR
This adds a Readme.md to each project directory with pointers to project
documentation in the wiki, and the drivers (if they exist). This will
help with some autogenerated doc in the wiki, that is generated with the
innovatily named "wiki_summary.sh" shell script that parses through
these Readme.md files, and generates a summary table.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Iacob Liviu Mihai <liviu.iacob@analog.com>
When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.
The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.
Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
The reconfiguration interface for the Stratix10 XCVR has a different
address width. Prepare the register map layout of the project to support
this new architecture.
All input and output delays should be referenced to a virtual clock.
If the input and output delays reference base clocks or PLL clocks rather than
virtual clocks, the intra- and inter-clock transfer clock uncertainties,
determined by derive_clock_uncertainty, are incorrectly applied to the I/O ports.
See mnl_timequest_cookbook.pdf for more info.
LBFFilho
Iulia Moldovan
PIoandan
laurent-19
LIacob106
PopPaul2021
AndrDragomir
Bogdan Luncan
Laszlo Nagy
Filip Gherman
Robin Getz
Adrian Costina
Sergiu Arpadi
Istvan Csomortani
Dragos Bogdan
AndreiGrozav