pluto_hdl_adi

Author	SHA1	Message	Date
laurentiu_popa	497a5f3f3a	projects/cn0561: Add FMC pin descripton for all carriers * Added txt description of all FMC pins used/unused * Updated constraint files with FMC pinout location Signed-off-by: laurentiu_popa <Laurentiu.Popa@analog.com>	2023-10-18 13:48:53 +03:00
Iulia Moldovan	1cac2d82e1	Add copyright and license to .xdc files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>	2023-07-25 11:03:02 +03:00
laurent-19	2ae09c9808	Check guidelines. Remove redundancies * Removed empty/commented lines * Regenerated Makefiles * Removed redundancies adc channels data width * Set data width 32-bit: max resolution and CRC header Signed-off-by: laurent-19 <laurentiu.popa@analog.com>	2023-03-29 15:08:07 +03:00
laurent-19	553774319a	projects/cn0561: Update design: spi trigger, ODR, spi hierch * Enabled ext_clk for PWM to use 96 MHz spi clk * Modified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK * Changed spi offload trigger signal: - replaced edge detect,sync_bits IPs with PWM trigger * Updated bd SPIE hierarchy, see library/spi_engine.tcl Signed-off-by: laurent-19 <laurentiu.popa@analog.com>	2023-03-29 15:08:07 +03:00
Stanca Pop	e71dbbd6f9	cn0561_zed: Initial commit	2022-05-11 17:30:26 +03:00