Iulia Moldovan
|
68461110aa
|
Replace link in license header from master to main
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
|
2024-01-16 16:48:45 +02:00 |
Bogdan Luncan
|
b1002cacbe
|
common: vmk180: Connected missing ss from spi
ad9081_fmca_ebz: vck190: system_top: Fixed spi signals indentation
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
|
2023-10-25 13:13:01 +03:00 |
|
Iulia Moldovan
|
c9a7d4d927
|
Add copyright and license to .tcl, .ttcl files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
|
2023-07-25 15:22:26 +03:00 |
|
Iulia Moldovan
|
1cac2d82e1
|
Add copyright and license to .xdc files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
|
2023-07-25 11:03:02 +03:00 |
|
Iulia Moldovan
|
28c06d505f
|
Add/edit copyright and license for .v, .sv files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
|
2023-07-11 15:17:41 +03:00 |
|
Iulia Moldovan
|
9977df074b
|
vmk180_system_bd.tcl: Fix issue with PMC_I2C_PERIPHERAL
* Issue appeared when updating to Vivado 2022.2
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
|
2023-03-09 09:53:41 +02:00 |
|
Iulia Moldovan
|
db94628cc6
|
library & projects: Update Makefiles
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
|
2023-01-27 11:54:05 +02:00 |
laurent-19
|
1eb5f4985b
|
projects/common: Add build files templates carriers. Modified Quartus Versions
The build files are available for the following carriers:
* intel: a10gx, a10soc, c5soc, de10nano, s10soc
* xilinx: coraz7s, kc705, kcu105, vc707, vc709,
vck190, vcu118, vcu128, vmk180,
zc702, zc706, zcu102, zed
* Added Makefiles, system_constr.sdc, system_qsys intel
* Added Makefiles, system_bd, system_constr xilinx
* de10nano, c5soc: Changed quartus version from 20.1.1 to 21.1.0
according to last commit update
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
|
2022-10-05 10:47:21 +03:00 |
|
laurent-19
|
6b94259a52
|
projects/common: Add system_top _project templates
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
projects/common: Correct code and modify according to guidelines
* Added spacing to ports declaration
* Corrected coding mistakes/misspelling
* Modified/added variables names
* Added seetings (intel) and removed specific optimization settings
* Added assignments to unassigned pins (gpios)
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
projects/common: Correct/Add missing wrapper ports and iobufs
* Added port in wrapper (mainly spi) according to base design file
* Added instances of iobufs where missing
* Corrected gpio assignments or added missing ones
* Corrected minor guidelines mistakes
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
ac701/system_top.v: Change top based on previous projects
* Looked at fmcomms1, fmcomms2 from hdl_2016_r1 and datasheet
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
projects/common: Modify templates to build without errors
* Changed path for adi_env.tcl
* Moved adi_project command before assign intel
* Removed unnecessary spi signals
* Added spi ports with default logic
* a10soc: Removed pl-ddr signals and ports
* ac701: system_bd: Modified mdio interface
system_project: Added adi_board, adiobuf sourcing
system_top: Removed hdmi, i2c, fanpwm, spdif ports
according to base design
* c5soc: Added version settings
Removed unused gpios
* microzed: system_bd: Enabled RTS1 to use FCLK
system_top: Removed hdmi, i2c, unused gpios
* vc709: Separated input from ouput gpio, according to bd
Removed unnecessary ports
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
projects/common: Delete microzed vmk_es templates
* Removed hp0 interconnect from cora base design
* Added extra line to files de10nano
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
|
2022-09-20 17:00:49 +03:00 |
AndrDragomir
|
72cf8f9b5d
|
projects/common: Add fmc connection files for every platform
|
2022-09-20 14:11:08 +03:00 |
Laszlo Nagy
|
833e5f0aff
|
common/vmk180: Initial version
|
2021-10-05 14:09:51 +03:00 |