Change necessary to build intel projects with different system_top verilog files.
This was patterned to ae09b8a1bb/projects/scripts/project-xilinx.mk (L70)
Signed-off-by: Jem Geronimo <Johnerasmusmari.Geronimo@analog.com>
* Removed the commercial JESD license and put the ADIBSD or GPL v2 like
for other Verilog files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
The generic project dependency list contains:
system_top*.v
system_bd.tcl
system_project.tcl
system_constr.xdc
This items will not be included in the auto generated makefiles. But
used as generic dependency.
This commit adds:
-wildcard check of system_constr*.xdc.
-wildcard check of system_constr*.tcl.
Add files CODEOWNERS, filled with owners per each hdl project and some IPs.
Specific code owners will be automatically added as reviewers, whenever new
PRs are opened, depending on affected folders/files from repo.
CODEOWNERS file can be different on each branch.
PULL_REQUEST_TEMPLATE.md content will populate all new PR description field.
Beside PR description, it contains a list of checkboxes, ensuring all
team members follow the same guidelines and enforce best practices.
PR Template applies for PRs against repository's default branch.
Both files were added in .github
Signed-off-by: Stefan Raus <Stefan.Raus@analog.com>
* Added copyright and license header
* Updated files on which it runs on
* SystemVerilog not to be supported, since now there are some pkg files
that do not have the format of a Verilog file, thus making the
checker to fail all the time -- which is not good
* Now it can run on files which contain JESD in their paths, because
now all of them have the copyright on the same line (but the
copyright inside the JESD license can't be checked yet by the script)
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
Due to nets being optimized at IP-level during the no-OOC synthesis flow,
constraints related to req_clk (request clock) were not being applied,
causing the design to not meet timing.
The fix considers the synchronous modes, appending the possible resulting
req_clk's names after the synthesis flow.
Due to grounded signals in the DMA_TYPE_SRC != DMA_TYPE_STREAM_AXI config.,
sync_rewind is removed during synthesis, even so, constraints were
trying to be applied to those nets.
To resolve this, sync_rewind block was moved to inside the generate.
Vivado seems to properly suppress "Empty list" warnings when the circuit does not exist because of a generate rule.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
- Removes the reset_tx_pll_and_datapath_in reset
- Connects gtreset_in to make use of the master reset found inside
the Transceiver Bridge IP
- Connects the necessary signals for the master reset between the
Transceiver Wizard and Transceiver Bridge
ad9209/vck190/system_top: Connect versal transceiver reset
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
The following CWs appeared (even in Vivado version 2021.2):
* CRITICAL WARNING: [BD 41-1356] Slave segment </sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM> is not assigned into address space </axi_rd_wr_combiner_logic/m_axi>. Please use Address Editor to either assign or exclude it.
* CRITICAL WARNING: [BD 41-1356] Slave segment </sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM> is not assigned into address space </axi_rd_wr_combiner_converter/m_axi>. Please use Address Editor to either assign or exclude it.
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
Add a list with make commands with the proper parameters for each devicetree
availible at the moment.
Signed-off-by: LIacob106 <liviu.iacob@analog.com>
* Updated the versions for repos and this solved the deprecated command
issue
* Changed the end message for when the guideline is not followed
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
The ADI_EXTRACT_PORTS variable is used to extract all the ports and nets properties of the desired IPS for the TransceiverToolbox and HighSpeedConverterToolbox to be later used for generating the json files automatically.
The ADI_SKIP_SYNTHESIS variable is used to stop the building process before the synthesis when used with Matlab support as it is not necessary at this point.
The ADI_MATLAB variable is used to choose the correct paths when building the design when using the HWA workflow.
docs/regmap/adi_regmap_adc.txt:
- add softspan to regmap
library/common/up_adc_channel.v
- update copyright year header
- add softspan to regmap
library/common/up_adc_common.v
- update minor version
Signed-off-by: John Erasmus Mari Geronimo <Johnerasmusmari.Geronimo@analog.com>
PopPaul2021
Jem Geronimo
Iulia Moldovan
AndreiGrozav
alin724
ladace
AndrDragomir
Filip Gherman
Stefan Raus
laurentiu_popa
Jorge Marques
Bogdan Luncan
LIacob106
PIoandan
Stanca Pop