AndreiGrozav
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235636a337
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fmcomms5_zc702: Enable AXI_SLICE for the DMA
This will increase the timing margin for the design
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2018-07-18 18:19:30 +03:00 |
Istvan Csomortani
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c9eaa43b1e
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fmcomms5: Update UP instantiations
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2017-04-21 15:10:44 +03:00 |
Rejeesh Kutty
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9b6dd27c23
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ad9361- delay initialization
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2017-03-15 12:06:59 -04:00 |
Adrian Costina
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d198caa621
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fmcomms2: Updated ZC702 design
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2015-09-25 18:15:40 +03:00 |
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Adrian Costina
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51b5e4ddc5
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fmcomms5: Moved the clock generation for dma transfer inside system_bd of the platform
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2015-04-02 22:29:17 +03:00 |
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Adrian Costina
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e58e9bc701
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fmcomms5: Updated zc702 project to the latest framework
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2015-03-31 17:44:09 +03:00 |
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Rejeesh Kutty
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9a36075324
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moved fmcomms5
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2014-05-19 13:49:49 -04:00 |