Commit Graph

2829 Commits (24b5de4438fc2a30778c6edcfb56647ede747cd8)

Author SHA1 Message Date
Adrian Costina dfe3258a4f adrv9009zu11eg: Add axi_sysid 2019-11-19 10:29:57 +02:00
Adrian Costina 81d3a9eb66 adrv9009zu11eg: Reduce SPI Clock speed to meet timing 2019-11-19 10:29:57 +02:00
Stanca Pop 4b380fe640 ad7768-1evb: Add coraz7s support 2019-11-15 14:35:00 +02:00
Stanca Pop 40d839df5f coraz7s: Initial commit 2019-11-15 14:35:00 +02:00
AndreiGrozav 514aadb54e m2k: Use dac trigger 2019-11-15 12:23:01 +00:00
Adrian Costina a589a2c7eb adrv9009_zu11eg_som: Change design partitioning
Create a structure similar with ADRV936x projects
2019-11-14 15:25:23 +02:00
Adrian Costina eab1e86544 adrv9364z7020: Rename *box project to *packrf 2019-10-29 16:07:08 +02:00
Adrian Costina de324526e3 adrv9361z7035: Rename *box project to *packrf 2019-10-29 16:07:08 +02:00
Stanca Pop fba7cac0c6 ad7768-1evb: Remove ADC2, update spi engine framework
The second ADC was removed from the project, as the EV-AD7768-1FMCZ evaluation
board contains only one ADC. Therefore, all the IPs related to the
second ADC have been removed, too.

The data width supported by the spi IPs has been changed from 8 bits to
32 bits, therefore the axis_upscaler(util_axis_upscale_v1_0) and the
m_axis_samples_24(AXI4-Stream Data Width Converter) are no more necessary,
so they have been removed from the design.

The 24 bits width data transfer between the s_axis of axi_ad77681_dma
(AXI DMA Controller) and the offload_sdi of the spi_engine_offload is now made
directly.
2019-10-28 12:00:23 +02:00
AndreiGrozav 4941d89fff cn0506_mii: Add support on a10soc 2019-10-18 19:09:04 +03:00
AndreiGrozav fbb3a154ff cn0506_mii: Add support on zcu102 2019-10-18 19:09:04 +03:00
AndreiGrozav 3cb2392711 cn0506_mii: Add support on zc706 2019-10-18 19:09:04 +03:00
AndreiGrozav e98951d282 cn0506_mii: Add support on zed 2019-10-18 19:09:04 +03:00
AndreiGrozav 8202c0025c cn0506_mii: Common design initial commit 2019-10-18 19:09:04 +03:00
AndreiGrozav 9323f4193c m2k: Clean old interrupt connection style 2019-10-18 18:28:01 +03:00
AndreiGrozav a4547a32b6 pluto: Clean old interrupt connections style 2019-10-18 18:28:01 +03:00
Stefan Raus fd4d32c408 projects/scripts/*xilinx*: Generate report utilization extra files
Add commands to generate one extra file with resource utilization, in CSV format.
New commands executes only if ADI_GENERATE_UTILIZATION env variable is set.
2019-10-18 13:42:34 +03:00
Istvan Csomortani 5a4726b356 adrv9364z7020: Fix interrupt concatenation 2019-10-17 15:09:48 +03:00
Istvan Csomortani f0f314f24b adrv9361z7035: Fix interrupt concatenation
None functional change, main goal is to increase consistancy in our
code base.
2019-10-17 15:09:48 +03:00
Istvan Csomortani 80333573c7 ad_fmclidar1_ebz/zcu102: Fix SYSREF input delay constraint
Add one clock cycle input delay for the SYSREF input,
to compensate the high propegation delay of device_clk_BUFG.
2019-10-17 09:59:23 +03:00
Istvan Csomortani 03bec4b49c ad_fmclidar1_ebz: Interchange SYSREF and DEV_CLK ports location
In ZCU102 LA01_CC_P|N are connected to regional clock, but in order to
receive a device clock properly we have to use pin which is connected
to a  global clock buffer. Luckily SYSREF is connected to global clock
pin; swap to port to receive the device clock correctly.

Also, swap the ports in both ZC706 and A10SOC carriers.
2019-10-17 09:59:23 +03:00
Istvan Csomortani 2cabf8d224 ad_fmclidar1_ebz: Move afe_iic definition to system_bd.tcl
In order to prevent platform specific variable usage in the common tcl
script, move the AFE I2C interface definition to system_bd.tcl
2019-10-17 09:59:23 +03:00
Istvan Csomortani b3e1cd2a15 ad_fmclidar1_ebz: Add support for ZCU102 2019-10-17 09:59:23 +03:00
Istvan Csomortani 3084a5d9aa ad_fmclidar1_ebz/a10soc: Fix the comment about the carrier re-work
The project is using the FMCA connector of the board. Make sure that all
the carrier re-work is related to the FMCA connector.
2019-10-17 09:58:52 +03:00
Stanca Pop 12c474ba13 ad7134: Change maximum data width from 24b to 32b 2019-10-16 17:35:24 +03:00
AndreiGrozav 3c46cc9347 dac_fmc_ebz: Add project info to sys_id
Add project device and mode info to sys_id custom string
2019-10-15 17:08:53 +03:00
AndreiGrozav 58b846faae dac_fmc_ebz: Add build time config option 2019-10-15 17:08:53 +03:00
Laszlo Nagy e22016de4c adrv9371/daq2/daq3:kcu105: patch GTH3 CPLL parameters
Update GTH3 parameters according to a 10Gbps link from the Transceiver
Wizard.
2019-10-08 10:38:46 +03:00
Arpadi 8895b08eb1 adrv9009_zu11eg_som: i2s mclk fix
mclk now generated by ps not axi clkgen ip. ADAU1761 expects a free
running clock and the i2s driver was switching the axi clkgen ip off
which was causing issues.
2019-10-03 17:30:57 +03:00
Istvan Csomortani 2344778dd8 ad_fmclidar1_ebz/a10soc: Initial commit
Add initial support for Arria 10 SOC carrier.
2019-10-02 15:32:17 +03:00
Istvan Csomortani 23d29e7a15 a10soc_system_qsys: sys_dma_clk clock_source inherit its clock frequency from its source 2019-10-02 15:32:17 +03:00
Istvan Csomortani af94487f57 adi_project_intel: Enable HPS internal timing
It's recommended to use this global assignment so the tool can make a
more in-depth timing analysis.
2019-10-02 15:32:17 +03:00
Istvan Csomortani bc2f916dfc a10soc: Synchronize resets to the reset source
Resets de-assertion should be synchronized to its associated clock.
2019-10-02 15:32:17 +03:00
StancaPop 9c9ce928d8
Merge pull request #346 from analogdevicesinc/spi_engine_trigger_update
spi_engine: Update pulse generation
2019-10-02 14:42:41 +03:00
Istvan Csomortani 75d263afc5 adi_project_xilinx: Add constraint files to constr_1 file set 2019-09-27 18:21:25 +03:00
Laszlo Nagy 64e54fda8d fmcomms5: remove clock skew handling
Use SSI clock from master as SSI clock of slave.
2019-09-27 17:52:10 +03:00
Stanca Pop 994bb6d0cf adaq7980: Software configurable trigger 2019-09-27 17:02:52 +03:00
Istvan Csomortani b174333fa2 project-xilinx.mk: Clean generated file by sysid 2019-09-27 13:16:19 +03:00
AndreiGrozav 7a685dd443 cn0506_rgmii/zcu102: Fix README typo 2019-09-26 16:33:45 +03:00
sarpadi 442b38033a sys_id: added catch to git status check
made error checking more general
2019-09-26 16:26:02 +03:00
AndreiGrozav 447434ace0 cn0506_rgmii: Add support for a10soc 2019-09-20 18:03:27 +03:00
AndreiGrozav 1138c48270 cn0506_rgmii: Add support for zcu102 2019-09-20 18:03:27 +03:00
AndreiGrozav f4f547715e cn0506_rgmii: Add support for zc706 2019-09-20 18:03:27 +03:00
AndreiGrozav 98fba87d8f cn0506_rgmii: Add support for zed 2019-09-20 18:03:27 +03:00
AndreiGrozav afd9420dab cn0506_rgmii: base design initial commit 2019-09-20 18:03:27 +03:00
Laszlo Nagy 7c3b4a5c73 ad9208_dual_ebz: Cleanup workarounds
Cleanup placement constraints and let the tool have more freedom to
place and route the design. This is possible only after balancing the
memory and system clocks.
2019-09-16 10:00:14 +03:00
Laszlo Nagy b7d48b8c74 common/vcu118: Balance clocks
Minimize skew on synchronous CDC timing paths between clocks originating
from the same MMCM source. (sys_mem_clk and sys_cpu_clk)
This is required mostly by the smart interconnect.
The CLOCK_DELAY_GROUP property must be applied directly to the output net of BUFGs.
2019-09-16 10:00:14 +03:00
AndreiGrozav 9f112640f3 m2k: Change constraint to match the new LA path 2019-09-13 11:55:11 +03:00
AndreiGrozav 5e08e2d548 project-xilinx.mk: Fix build condition
"prepare_incremental_compile" is defined as a phony target, but is also a
prerequisite of a real target. This will lead to a complete project build
every time make is called.
To fix the issue the functionality of prepare_incremental_compile target
was included in the generic project build target.
2019-09-12 13:23:09 +03:00
Istvan Csomortani 16a797198f ad_fmclidar1_ebz/common: Fix m_dest_axi_aresetn source 2019-08-29 08:59:56 +03:00