2 Commits (251ea9471c175496aaa71c800752d1a77d8f624e)

Author	SHA1	Message	Date
Laszlo Nagy	3f94fec620	axi_dmac/dma_write_tb: added data integrity check ... Added passing condition checking. Added variable request sizes	2018-05-03 14:49:06 +02:00
Lars-Peter Clausen	24d17e8bcc	axi_dmac: Add transfer testbenches ... Add simple transfer testbenches that test the read and write to AXI memory paths of the DMAC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2018-05-03 14:49:06 +02:00