4f0d7bd6eb
util_wfifo: read after write is complete
2016-07-11 09:59:31 -04:00
832efdc99c
hdlmake updates
2016-07-08 13:58:56 -04:00
7a03d44e4e
adxcvr- clock buffers are removed
2016-07-08 13:57:27 -04:00
20ac95b1ec
adxcvr- initial commit
2016-07-08 13:57:27 -04:00
48762519b5
make updates
2016-07-06 15:02:00 -04:00
427cc84bb2
axi_ad7616: Rename the physical interface signals to rx_*
...
No functional modification.
2016-07-01 14:45:23 +03:00
d931b2ee64
ad9162 core verilog files
2016-06-30 10:24:01 -04:00
8d558b2538
make: Update Make files
2016-06-29 14:50:07 +03:00
18e28b01fd
axi_ad7616: Add burst counter to the parallel interface
...
With this counter the parallel logic supports the burst sequencer.
2016-06-29 14:17:28 +03:00
e6494b9a74
axi_ad7616: Change the DMA interface type to Write FIFO
2016-06-29 14:11:02 +03:00
64633e519c
Merge remote-tracking branch 'origin/dev_ad7616' into dev
2016-06-29 12:32:39 +03:00
cdf01a492e
library/axi_dacfifo: Update the bypass logic
...
The bypass logic is located between the AXI read controller and the
DAC CDC fifo. When the bypass is enabled the DMAC destination interface
must be clocked with the PL_DDR controller's ui_clk. This way it can easily
switch between the AXI read's stream and DMAC's stream interface.
2016-06-22 12:24:54 +03:00
def47dd536
interfaces: added xcvr interfaces
2016-06-17 12:00:15 -04:00
36fbf4fc42
util_adxcvr: shared xcvr cores
2016-06-17 11:59:42 -04:00
87cf13b0ef
util_adxcvr- system verilog interfaces
2016-06-16 16:41:43 -04:00
80ce7aeb66
util_adxcvr- updates
2016-06-16 16:40:57 -04:00
7c762f63a8
library/axi_dacfifo: Fix the control logic of the write side
...
Fix the control logic for the AXI write transactions.
2016-06-15 13:49:00 +03:00
d5ce137c55
library/axi_dacfifo: Fix reset for a few registers
2016-06-15 13:49:00 +03:00
10090a296e
library/axi_dacfifo: Cosmetic changes
...
Rename a few registers and improve consistency.
2016-06-15 13:49:00 +03:00
7485d27d37
ad9361/altera- device-family variable
2016-06-14 12:28:13 -04:00
5d437083cc
ad9361/altera- a10+ only
2016-06-14 12:19:54 -04:00
dc45287b14
util_adxcvr- added
2016-06-14 12:19:18 -04:00
c19ed4c8ef
axi_hdmi_tx_core: Fixed embedded sync synchronization signals
2016-06-14 14:30:28 +03:00
aee38e1cc9
up_hdmi_tx: Fixed data path width
2016-06-14 14:27:03 +03:00
27fd5f5bdc
modified prbs7 and prbs15 gereration code
2016-06-13 14:44:03 -04:00
83dd7e91c4
deleted pn23 and pn 31, data width yet to be modified
2016-06-13 14:44:03 -04:00
341b7badee
library/scripts: Remove all autogenerated interface in adi_ip_properties_lite
...
There are a few IP, which is configured by using just the adi_ip_properties_lite
process, therefor the remove_all_bus_interface will be called in the end of that
process, to make sure that all the autogenerated interfaces are deleted during the
IP properties setup.
2016-06-10 15:08:05 +03:00
9d1ae436b1
common/util_pulse_gen: Rename the ad_tdd_sync module
2016-06-09 10:07:47 +03:00
abe837e608
util_rfifo: Set an offset for the write addres
2016-06-02 17:34:29 +03:00
c293c04634
hdl make updates
2016-06-01 13:53:09 -04:00
3832f2669e
axi_jesd_xcvr: support tx/rx disable
2016-06-01 13:48:51 -04:00
54f398cc36
ad9371-hw- add dsp slice
2016-06-01 13:48:51 -04:00
e1495b89f9
axi_dacfifo: Cosmetic changes
2016-05-27 14:13:55 +03:00
c724c027c4
axi_dacfifo: Fix the synchronizers
2016-05-27 14:13:55 +03:00
183c67aca0
axi_dacfifo: Update the axi write controller
...
Do some refactoring and add a DMA beat counter.
2016-05-27 14:13:55 +03:00
8caa783f5c
axi_dacfifo: Update the constraints
2016-05-27 14:13:55 +03:00
3b6a36e3e2
axi_dacfifo: Increase the ASYM_MEM depth in the DAC side
...
Increase the asymetric memory depth on the DAC side. Increase the
data width of the grey coder and decoder.
The controller fills up the CDC memory with three AXI burst, to prevent
underflow on the wrap arounds.
2016-05-27 14:13:55 +03:00
c8d4f956e7
axi_dacfifo: Update the read back logic
...
Update the readback logic of the FIFO. The controller uses a
relative address counter, which counts the DMA beats. The readback
logic uses the last value of that counter to define the wrapping
address. The aditional data from the last AXI burst, if there is any,
will be dropped.
2016-05-27 14:13:55 +03:00
88e0cfec42
axi_dacfifo: The AXI read and write have the same properties
...
AXI read and AXI write channel have the same SIZE and LENGTH.
2016-05-27 14:13:55 +03:00
aca3038919
axi_dacfifo: No overflow for DAC
2016-05-27 14:13:55 +03:00
81ade7f26c
axi_dacfifo: Fix resets
...
DMA side: axi_resetn is used to reset the address counters
DAC side: GT tx_rst is used to reset the last_address register
2016-05-27 14:13:55 +03:00
578376c8fe
axi_dacfifo: Add bypass logic
2016-05-27 14:13:55 +03:00
f10c1e6e93
axi_hdmi_tx: Remove hdmi_full_range register
2016-05-27 14:04:40 +03:00
05ac271aff
daq3/a10gx- qsys modifications
2016-05-24 03:15:24 -04:00
d254fa841b
library- altera updates
2016-05-23 10:55:07 -04:00
3f00614bc7
axi_jesd_xcvr: rx/tx only select
2016-05-20 16:13:36 -04:00
f1a603a3b1
ad9371- altera ip
2016-05-20 15:16:36 -04:00
09520709b0
make updates
2016-05-20 12:35:45 -04:00
b5b05bb9d1
axi_ad9371: added
2016-05-20 11:41:54 -04:00
bf0b90229a
rfifo/wfifo- qsys ip
2016-05-18 13:24:13 -04:00
Rejeesh Kutty
Istvan Csomortani
Shrutika Redkar
AndreiGrozav