e94df1d7da
library/axi_ad7768: Data valid signal updates
...
If the sampling clock is lower than dclk*number_of_active_lines*32 the interface should wait for the next adc_ready signal to reset the counter.
The adc_valid_p signal should be set high just for a clock period after the sample was captured.
2023-03-01 15:52:05 +02:00
db94628cc6
library & projects: Update Makefiles
...
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-01-27 11:54:05 +02:00
22fbb05256
Update IPs based on up_adc_common changes
2023-01-12 13:09:35 +02:00
eb663876d7
axi_ad7768: modified adc_format values and crc_err flag has to be RW1C
2022-11-15 15:43:46 +02:00
28ace647d1
up_adc_common: Update IPs and adi_regmap_adc definition file to latest up_adc_common module
2022-10-05 14:56:36 +03:00
775a23ebf2
up_adc_channel: Update IPs and adi_regmap_adc definition file to latest up_adc_channel module
2022-10-05 14:27:51 +03:00
cc18f90579
Added axi_ad7768 IP Core ( #989 )
...
* projects/ad7768evb: Initial commit with axi_ad7768 IP
* library/axi_ad7768: Initial commit for AD7768/AD7768-4
2022-08-24 16:57:14 +03:00
PopPaul2021
Iulia Moldovan
AndreiGrozav
alin724
PopPaul2021