zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
4,495 Commits
1 Branch
0 Tags
23 MiB
Commit Graph

2 Commits (297940d5d9cec65e7f9d1edb6a1bc7d48deca5f7)

Author SHA1 Message Date
AndreiGrozav 03e744f0f1 daq1_zed: Lower the adc and daq clock to 450MHz 
The FPGA fabric on zedboard is a -1 speadgrade (max bufg clk 464MHz)
 2017-10-04 13:01:14 +01:00
AndreiGrozav 6b897dabe5 daq1_zed: Initial commit 2017-07-31 14:26:23 +03:00