377247a434
Regenerate project Makefiles using the new shared Makefile includes
...
This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.
It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
425e803364
license: Fix a spelling mistake
2018-04-11 15:09:54 +03:00
b54dab33e0
Make: Update makefiles
2017-11-20 14:27:39 +02:00
de5a21af80
daq2: A10GX, added additional interconnect pipelining
2017-10-23 16:39:58 +01:00
aa6af4e522
daq2: A10GX, added extra pipelining in the interconnect in order to improve timing
2017-10-20 13:45:05 +01:00
083962450a
daq2: A10GX, connect dac_fifo_bypass to gpio
2017-10-19 16:07:18 +03:00
72d9c1c6f2
daq2: A10GX, added dac fifo
2017-10-11 12:52:15 +03:00
ee01ea3736
daq2/a10gx: Add cfi_flash to qsys
...
+ Add cfi_flash to qsys
+ Set nios reset vector to cfi_flash
2017-10-04 11:30:29 +01:00
17d3e3c64b
daq2: daq2_qsys.tcl: Convert to ADI JESD204
...
Convert the DAQ2 project for Intel/Altera platforms to the ADI JESD204
framework.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:21:42 +02:00
d1bab7ddb9
hdlmake.pl- updates
2017-06-06 16:10:05 -04:00
3f92381bd0
daq2/a10gx- project/constraint updates
2017-06-06 16:09:15 -04:00
dd48929327
hdlmake.pl - updates
2017-06-06 12:25:35 -04:00
50cdb6db67
Merge branch 'jesd204' into dev
2017-05-31 20:44:32 +03:00
84b2ad51e2
license: Add some clarification to the header license
2017-05-31 18:18:56 +03:00
85ebd3ca01
license: Update license terms in hdl source files
...
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
4c998d1e18
make: Update make files
2017-05-25 15:12:17 +03:00
01aea161fa
Create CDC helper library
...
Move the CDC helper modules to a dedicated helper modules. This makes it
possible to reference them without having to use file paths that go outside
of the referencing project's directory.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
9055774795
all: Update license for all hdl source files
...
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.
New license looks as follows:
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.
Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
(at the option of the user):
1. The GNU General Public License version 2 as published by the
Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
OR
2. An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
c4b4bdc415
daq2/a10gx- constraints remove 16.0
2017-05-16 10:09:42 -04:00
cfcb269d38
a10gx- change ddr to 1G
2017-05-15 09:32:36 -04:00
942d69a30c
Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU
2017-04-18 10:57:16 +03:00
1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
8063ba2b66
make updates
2017-03-20 16:05:18 -04:00
b78e9d8c27
daq2_a10gx: Set XCVR Tx/RX clk/data voltage levels at 1V
2017-03-01 11:32:17 +02:00
85ff496c12
daq2/a10gx- gpio match with others
2017-02-01 20:54:56 -05:00
4a783d523d
projects/altera* - default & common qsys commands
2016-12-20 16:27:44 -05:00
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
cb97bc500a
hdlmake updates
2016-10-17 16:29:57 -04:00
5bb77109ca
daq2/a10gx- make fix
2016-10-10 13:03:44 -04:00
905e29eb01
hdlmake- altera
2016-10-10 12:55:55 -04:00
16ee1336c3
Makefile: Update make files
2016-09-15 11:41:06 +03:00
5df30ac6b0
daq2/a10gx- xcvr sharing
2016-09-12 14:57:50 -04:00
2f9ac4a342
altera- qsys-script does not support most tcl commands
2016-08-30 11:50:36 -04:00
c6f4def93d
altera- make mmu a make switch
2016-08-08 11:54:51 -04:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
f784557895
lib_refactoring: IOBUF is a Xilinx macro, no need to use with Altera
2016-08-08 15:06:34 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
e42b4ea378
hdlmake- updates
2016-08-04 13:28:25 -04:00
eaf4d4a19d
makefile updates
2016-06-10 14:26:14 -04:00
468800bb38
daq2/a10gx- makefile update
2016-06-07 14:06:42 -04:00
625052f46e
daq2/a10gx- qsys updates
2016-06-07 12:28:04 -04:00
ae1dd1d58e
daq2/a10gx- qsys updates
2016-06-07 12:28:04 -04:00
3516ec28b7
daq2/a10gx- qsys updates
2016-06-07 12:28:04 -04:00
7a4a7edfba
daq2/a10gx: 10AX115S3F45E2SGE3 version
2016-04-20 16:07:41 -04:00
679d471d75
Merge branch 'hdl_2016_r1' into dev
...
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
657144d9a7
a10gx: Updated base design and DAQ2 to the new revision of the a10gx board
...
- tried using ATX PLL and fPLL for TX transceiver clocks, but could not get them to lock
- CMU PLL works correctly as temporary solution
2016-03-28 13:21:36 +03:00
377461e0d4
Merge branch 'hdl_2015_r2' into dev
2016-02-19 14:15:27 +02:00
ad9ecbbbb6
daq2: Updated a10gx project to quartus 15.1.1
2016-02-05 17:43:05 +02:00
da2e1bdc9a
daq2/a10gx: 32bits generic gpio
2015-12-11 11:50:26 -05:00
2309c4d83c
Makefiles: Removed " from path
2015-11-27 14:02:46 +02:00
Lars-Peter Clausen
Istvan Csomortani
Adrian Costina
STEVE KRAVATSKY
Rejeesh Kutty
AndreiGrozav