Istvan Csomortani
2a17ce275c
axi_ad7616: Control inputs are controlled through GPIO
...
The following control inputs are controlled through GPIO: reset_n, seq_en, hw_rngsel, chsel, crcen, burst and os.
2016-01-25 17:50:50 +02:00
Istvan Csomortani
4b962e8d72
spi_engine: The width of the counters depend on the current DATA_WIDTH
2016-01-20 15:44:06 +02:00
Istvan Csomortani
14f7027793
ad7616_sdz: Move the context switching to system_project.tcl
2016-01-19 11:34:28 +02:00
Istvan Csomortani
c29dd8fad5
axi_ad7616: Fix Makefile
2015-12-21 19:39:58 +02:00
Istvan Csomortani
0b55325db9
axi_ad7616: Fix IP packaging script
2015-12-21 19:39:14 +02:00
Istvan Csomortani
17e7d1b86f
ad7616: Add Makefiles
2015-12-21 17:09:42 +02:00
Istvan Csomortani
ee4d5af12e
ad7616_sdz: Update the project
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+ Fix system_top.v
+ Finish up the common block design
+ Fix system_project.tcl
2015-12-14 16:02:38 +02:00
Istvan Csomortani
8ae9de8fba
axi_ad7616: Update core
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+ Both the data width and number of SDI lines are configurable
+ SER1W line is hardware configurable, it was removed from the IP
+ Add 'Hardware mode' support for the controller
2015-12-14 16:00:56 +02:00
Istvan Csomortani
4e57170384
spi_engine: Update SPI Engine frame work
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+ data width and number of SDI lines are configurable
+ axi_spi_engine module can have two different type of memory map interface (S_AXI or UP)
2015-12-14 15:57:54 +02:00
Istvan Csomortani
29a0f27cd1
ad_edge_detect: Add a flop to output, reset is active high
2015-12-14 15:40:29 +02:00
Istvan Csomortani
f4e3523390
ad7616_sdz: Update IO constraints
2015-12-14 15:34:56 +02:00
Istvan Csomortani
d6eae81bc1
axi_ad7616: Add the control module to the core, finish up SPI integration
2015-11-13 18:14:21 +02:00
Istvan Csomortani
952a491f59
axi_ad7616: Add spi engine to the core
2015-11-12 16:12:16 +02:00
Istvan Csomortani
e4927887fd
spi_engine_offload: Add sync_bits to the IP files list
2015-11-10 13:35:15 +02:00
Istvan Csomortani
229cd079b9
spi_engine: Fix to support multiple SDI lines
2015-11-10 13:34:29 +02:00
Istvan Csomortani
64d1948ea0
axi_ad7616: Initial commit
2015-11-10 13:32:56 +02:00
Istvan Csomortani
214adbfd85
ad7616_sdz_zc706: Add board related IO's to system top.
2015-11-09 10:51:46 +02:00
Istvan Csomortani
27266c59ee
ad7616_sdz: Add project source files
2015-11-03 15:03:35 +02:00
Istvan Csomortani
cf58110a98
Merge branch 'dev' into dev_ad7616
2015-11-03 14:07:48 +02:00
Lars-Peter Clausen
a0039ed4fe
ccfmc: Launch HDMI data on falling edge
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The ADV7511 captures data on the rising edge, so make sure to launch data
on the falling edge. This fixes some issues with image stability.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-11-03 10:59:13 +01:00
Lars-Peter Clausen
acd9efc528
axi_hdmi_tx: Add parameter to configure the output clock polarity
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In order to maximize the window where it is safe to capture data we ideally
want to launch data on the opposite edge to which it is captured. Since the
edge on which data is captured depends on the connected device add a
parameter that allows to configure the launching edge.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-11-03 10:59:13 +01:00
Rejeesh Kutty
6dddac5d94
ccfmc- missing board io
2015-11-02 15:45:14 -05:00
Rejeesh Kutty
cafc80c829
fmcadc5: add programmable io delay
2015-11-02 12:10:18 -05:00
Istvan Csomortani
a147acd791
spi_engine: Add support for multiple SDI lines.
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By changing the parameter called SDI_DATA_WIDTH the spi framework can support multiple SDI lines.
The supported number of SDI lines are: 1, 2, 3 and 4.
2015-11-02 18:42:55 +02:00
Rejeesh Kutty
8b95520767
pzsdr/ccfmc- add loopback gpio/gt cores
2015-10-30 18:48:26 -04:00
Rejeesh Kutty
88568c21e1
util_gtlb: updates for latest axi_jesd_gt
2015-10-30 18:47:36 -04:00
Rejeesh Kutty
92b7570864
pzsdr/ccfmc- add ad9517 signals
2015-10-30 10:50:53 -04:00
Rejeesh Kutty
b3cb84cf91
fmcadc5- added ila
2015-10-29 16:48:21 -04:00
Rejeesh Kutty
24d76c610a
fmcadc5- fix core connections
2015-10-29 16:47:56 -04:00
Rejeesh Kutty
ac4091e19e
fmcadc4- add monitor fifo
2015-10-27 14:52:02 -04:00
Rejeesh Kutty
2b6ae00a44
library: add mfifo
2015-10-27 14:52:02 -04:00
Adrian Costina
b5d3d0bd13
usb_fx3: Added axi_usb_fx3 core and DMA to the project
2015-10-27 09:41:18 +02:00
Rejeesh Kutty
748a2bc87a
fmcadc4- add ila for zc706 only
2015-10-23 14:32:35 -04:00
Rejeesh Kutty
b2d0f5c56e
fmcadc4- use the same source/name for clocks
2015-10-23 14:32:35 -04:00
Rejeesh Kutty
f1ed27105f
library/common- reset fix
2015-10-23 14:32:35 -04:00
Adrian Costina
32b3cfd8b9
axi_usb_fx3: Initial commit of the core with interface stub
2015-10-23 13:27:00 +03:00
Adrian Costina
9d2b8809df
Makefiles: Updated Makefiles
2015-10-23 10:44:27 +03:00
Rejeesh Kutty
cb2bda48c0
fmcadc5- gt/ip updates
2015-10-19 09:31:32 -04:00
Rejeesh Kutty
ed918ec119
imageon - keeping scripts happy
2015-10-16 15:04:02 -04:00
Rejeesh Kutty
e14e9294c5
project-names -- variables causes scripts to fail- too much parsing
2015-10-16 14:13:56 -04:00
Istvan Csomortani
36dd6427fe
pzsdr: Add untracked Makefiles
2015-10-16 13:58:36 +03:00
Istvan Csomortani
6fb56079ee
library/util_gtlb: Add Makefile
2015-10-16 13:58:01 +03:00
Istvan Csomortani
8ecdb4a4ca
library/tdd_control: Add common registers to the register map and fix init value of a register
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+ Software in general needs to have access to the VERSION register.
+ tdd_sync_d3 registers init value should be 1'b0
2015-10-16 11:57:54 +03:00
Istvan Csomortani
bbdc693954
pzsdr/all: Update Makefile
2015-10-16 11:57:51 +03:00
Rejeesh Kutty
44568f1f64
util_jesd_gt: bad idea, it is needed for ipi
2015-10-15 11:13:08 -04:00
Rejeesh Kutty
08777ca566
fmcadc5- latest board changes
2015-10-15 10:46:07 -04:00
Rejeesh Kutty
030485de28
fmcadc5- regulators need a switching ref clock?
2015-10-15 10:46:07 -04:00
Rejeesh Kutty
f966f79e5f
fmcadc5- regulators need a switching ref clock?
2015-10-15 10:46:07 -04:00
Rejeesh Kutty
a6ff1b13fc
util_jesd_gt- remove unused parameters
2015-10-15 10:46:07 -04:00
Istvan Csomortani
21737ad7b8
fmcomms2/zc706pr: Update the fifo interface of the PR module
2015-10-13 11:37:44 +03:00