Commit Graph

118 Commits (2b108c63db90fac5aaa92c838043ad52c31f862e)

Author SHA1 Message Date
Lars-Peter Clausen b20714bae2 Regenerate project top-level Makefiles
Removes a lot of boilerplate code.

Using the new scheme it is possible to add new projects or sub-projects
without having to re-generate any existing Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 377247a434 Regenerate project Makefiles using the new shared Makefile includes
This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.

It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Istvan Csomortani a740b6012f Make: Use $(MAKE) for recursive make commands
This commit should resolve the issue #64.

Recursive make commands should always use the variable MAKE, not the explicit
command name ‘make’.
2018-03-07 07:40:19 +00:00
Adrian Costina b54dab33e0 Make: Update makefiles 2017-11-20 14:27:39 +02:00
Istvan Csomortani d9acdb8092 usdrx1/a10gx: Add external flash support 2017-10-06 08:47:24 +01:00
Lars-Peter Clausen f0655e63a6 avl_adxcvr: Derive PLL and core clock frequency from lane rate
The PLL frequency must be half of the lane rate and the core clock rate
must be lane rate divided by 40. There is no other option, otherwise things
wont work.

Instead of having to manually specify PLL and core clock frequency derive
them in the transceiver script. This reduces the risk of accidental
misconfiguration.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 15:11:08 +02:00
Rejeesh Kutty ef290ef484 hdlmake.pl updates 2017-06-15 11:42:44 -04:00
Rejeesh Kutty e33e6a84f4 a5gt/a5soc - removed 2017-06-15 11:41:28 -04:00
Rejeesh Kutty 2649458b6d hdlmake.pl updates 2017-06-15 10:21:57 -04:00
Rejeesh Kutty fd0c7f1b1c usdrx1/a10gx- updated to a10gx 2017-06-15 10:21:57 -04:00
Rejeesh Kutty 0311ed411c usdrx1/a10gx- added 2017-06-15 10:21:57 -04:00
Rejeesh Kutty 6decba3c3b hdlmake.pl updates 2017-06-09 16:23:17 -04:00
Adrian Costina b7ca17f02b scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
Istvan Csomortani 50cdb6db67 Merge branch 'jesd204' into dev 2017-05-31 20:44:32 +03:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 4c998d1e18 make: Update make files 2017-05-25 15:12:17 +03:00
Lars-Peter Clausen 01aea161fa Create CDC helper library
Move the CDC helper modules to a dedicated helper modules. This makes it
possible to reference them without having to use file paths that go outside
of the referencing project's directory.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Rejeesh Kutty f09b902609 usdrx1- spi/mlo fixes 2017-05-22 13:22:44 -04:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Rejeesh Kutty ebeebdddf0 altera- infer latest versions 2017-05-12 13:40:14 -04:00
Adrian Costina 942d69a30c Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
Adrian Costina ebc04bcd9c usdrx1: ip automatic version update 2017-04-14 17:16:35 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Rejeesh Kutty 8063ba2b66 make updates 2017-03-20 16:05:18 -04:00
AndreiGrozav e736504e0f fmcjesdadc1, usdrx1: Using the same clock in rx_data path 2017-03-10 14:26:51 +02:00
Rejeesh Kutty fb4a583613 projects/system_bd- adc/dac fifo board designs 2017-02-27 16:06:39 -05:00
Rejeesh Kutty edd5e9570f file renamed; sed output; fingers crossed 2017-02-22 15:56:37 -05:00
Istvan Csomortani 5fa6dba333 Make: Update Makefiles 2017-02-10 16:32:58 +02:00
Rejeesh Kutty aa6c94c993 usdrx1/a5gt: ddr3 use ip constraints 2016-12-22 14:14:21 -05:00
Rejeesh Kutty 4a783d523d projects/altera* - default & common qsys commands 2016-12-20 16:27:44 -05:00
Istvan Csomortani da7f4608a8 fmcjesdadc1/usdrx1: Clean up the mess
Delete accidentally commited generated files.
2016-12-19 15:35:20 +00:00
Istvan Csomortani f47863bbcf usdrx1: Integrate ad_syref_gen into the project 2016-12-19 14:36:01 +00:00
AndreiGrozav d962614000 usdrx1/zc706: Disabele axi_spi constraint file
The interface ports of the AXI SPI IP are not connected
  directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:23:51 +02:00
Adrian Costina 8ebc8fe4e2 updated makefiles 2016-12-09 23:06:41 +02:00
Rejeesh Kutty f799c40cf0 usdrx1/a5gt- xcvr interface changes 2016-12-08 16:05:23 -05:00
Rejeesh Kutty c114888956 usdrx1- updates 2016-12-08 16:05:23 -05:00
Rejeesh Kutty 170c781d02 hdlmake.pl- updates 2016-12-01 13:52:11 -05:00
Adrian Costina 284fbac571 usdrx1: Xcvr updates, so that the channel parameters are correctly configured from boot time 2016-11-28 14:16:07 +02:00
Adrian Costina 7c541c704a usdrx1: ZC706, Update project to the new GT framework 2016-10-14 18:08:08 +03:00
Rejeesh Kutty 905e29eb01 hdlmake- altera 2016-10-10 12:55:55 -04:00
Istvan Csomortani 16ee1336c3 Makefile: Update make files 2016-09-15 11:41:06 +03:00
Adrian Costina 0b0aa8e6c0 Makefile: Add MMU option to altera makefiles 2016-08-11 17:46:54 +03:00
Adrian Costina d60bce654c Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools 2016-08-05 15:16:04 +03:00
Rejeesh Kutty e42b4ea378 hdlmake- updates 2016-08-04 13:28:25 -04:00
Istvan Csomortani 7ca8e10004 make: Update Make files 2016-08-01 14:24:48 +03:00
Rejeesh Kutty eaf4d4a19d makefile updates 2016-06-10 14:26:14 -04:00
Istvan Csomortani b0538a03a2 Make: Update 2016-05-06 16:44:24 +03:00
Istvan Csomortani 4863a04132 axi_adc/dacfifo: Split the intergration script file
Split the integration script file into two separate script files. Rename the
integration processes names to be more meaningful.
2016-05-05 09:53:55 +03:00