2b4b9d7bab
daq2: Disable start synchronization for the ADC DMA
2017-10-31 17:16:08 +02:00
e3ea51ade3
avl_dacfifo: Refactor the fifo
...
+ Build both the read and write logic around an FSM
+ Consistent naming of registers and wires
+ Add support for burst lenghts higher than one, current burst lenght
is 64
+ Fix all the bugs, and make it work (first bring up with
adrv9371x/a10soc)
2017-10-31 14:30:06 +00:00
5b9e4cb692
daq2/zcu102: Pin Swap for ZCU102 Rev1.0
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2017-10-30 11:09:20 +00:00
22df03f9a4
daq3: A10GX, overconstrained failing paths
2017-10-28 08:21:50 +01:00
fe1adb6e4f
daq3: A10GX, updated to the ADI JESD204
...
- changed lane rate to 12.33Gbps
- added dac fifo
2017-10-25 14:45:27 +01:00
de5a21af80
daq2: A10GX, added additional interconnect pipelining
2017-10-23 16:39:58 +01:00
e8bab0b45f
adi_env: Normalize environment variables
...
If the ADI_HDL_DIR or ADI_PHDL_DIR are set on Windows platforms, an
invalid TCL character (e.g. backslash) may be used as a file separator,
causing issues with the build / library scripts.
Normalize the paths before using them as global TCL variables.
2017-10-23 12:15:14 +01:00
37323e3444
adrv9371x: A10GX, added extra pipelining in the interconnect in order to improve timing
2017-10-20 13:46:22 +01:00
aa6af4e522
daq2: A10GX, added extra pipelining in the interconnect in order to improve timing
2017-10-20 13:45:05 +01:00
083962450a
daq2: A10GX, connect dac_fifo_bypass to gpio
2017-10-19 16:07:18 +03:00
e43056455c
daq2: A10SOC, added dac fifo
2017-10-12 14:16:05 +03:00
72d9c1c6f2
daq2: A10GX, added dac fifo
2017-10-11 12:52:15 +03:00
d9acdb8092
usdrx1/a10gx: Add external flash support
2017-10-06 08:47:24 +01:00
baf8ec09a3
fmcjesdadc1/a10gx: Add external flash support
2017-10-06 08:46:22 +01:00
df70a6605c
daq3/a10gx: Add external falsh support
2017-10-06 08:45:33 +01:00
be4e02aed9
adrv9371x/a10gx: Add external flash support
2017-10-06 08:43:58 +01:00
d690a614c1
a10gx: Force all used tiles to high speed, in order to improve timing
2017-10-04 16:16:00 +01:00
03e744f0f1
daq1_zed: Lower the adc and daq clock to 450MHz
...
The FPGA fabric on zedboard is a -1 speadgrade (max bufg clk 464MHz)
2017-10-04 13:01:14 +01:00
7a3c4ab81f
arradio: Changed ADC DMA buswidth connection to the DDR to 128 bits
...
This fixes the bandwidth issue when data is streamed from the DDR and the system works at 61.44 MSPS
2017-10-04 13:01:14 +01:00
ee01ea3736
daq2/a10gx: Add cfi_flash to qsys
...
+ Add cfi_flash to qsys
+ Set nios reset vector to cfi_flash
2017-10-04 11:30:29 +01:00
a33f3178c2
adrv9371x/a10soc: For receive paths SYNC_TRANSFER must be enabled
2017-10-04 11:29:09 +01:00
899b8436ad
arradio: Fix the last incorrect merge
2017-10-03 09:15:45 +01:00
89bd8b44d4
Merge branch 'dev' into hdl_2017_r1
2017-09-26 07:42:19 +01:00
256dd87dd2
common/microzed: Enable PS CLK1 = 200MHz
2017-09-25 15:16:58 +03:00
07f3295638
common/a10soc: Update configuration for emif plddr4 IP
2017-09-25 08:57:26 +01:00
700ed156ab
[axi|avl]_dacfifo: Create a separate bypass module for altera/xilinx
2017-09-25 08:56:40 +01:00
3a47567f9c
common/a10gx: Chance SPI frequency from 128KHz to 10 MHz
2017-09-19 18:01:18 +03:00
cafa811c74
adrv9379: Change the DMA clock to 250
2017-09-11 16:52:44 +03:00
58572d746c
arradio/c5soc- rd10102013_979 fix
2017-09-05 12:52:41 -04:00
c3aa3e8a9c
adrv9371: a10soc: Whitespace cleanup
...
Remove some extra end-of-line whitespace.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-05 13:47:49 +02:00
6736aaeca1
arradio- add control/status ports
2017-09-01 14:39:18 -04:00
bb73e7a40f
arradio- add control/status ports
2017-09-01 14:39:18 -04:00
6ce4494002
adrv9379: Initial commit
2017-09-01 17:28:04 +03:00
cb2fd6af73
dm2k: Drive the ADC DMA valid from the trigger extracting core
2017-08-30 18:28:52 +03:00
5bc927ff94
adrv9364/ccbox- input rf protection
2017-08-25 13:30:46 -04:00
dc0a71920c
adrv9361/ccbox- sort gpio - accidental multiple drivers
2017-08-25 13:30:46 -04:00
fd8b524953
adrv9361-ccbox/ccfmc- adl5904/gpio updates
2017-08-25 11:23:56 -04:00
4050f5ae58
adrv9361- add adl5904
2017-08-24 15:47:17 -04:00
e4988aa131
adrv9371x: altera: Convert to ADI JESD204
...
Convert the ADRV9371 project for Intel/Altera platforms to the ADI JESD204
framework.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 17:55:10 +02:00
d05ed29212
adrv9371x_zcu102: Initial commit
2017-08-22 15:48:03 +03:00
c0da4e6192
adrv9371x_kcu105: Initial commit
2017-08-22 15:41:49 +03:00
1d67036305
adrv9371x/common: Remove ila_adc and ila_os_adc
2017-08-22 15:37:59 +03:00
6fa45bb378
adrv9371x/common: Fix axi_ad9371_dacfifo/dac_rst assignamen
2017-08-22 15:37:59 +03:00
a64998c3ff
adrv9371x: Separate ps7 assignaments from common
...
Move the assignaments/connections for ps7 from common/adrv9371_bd
to zc706/system_bd
2017-08-22 15:37:59 +03:00
b7ce81686a
common/zcu102: Fix ps8 ref clock 0 frequency assignament
2017-08-22 15:37:59 +03:00
41e247d426
common/zcu102: Add gpio_t connections
2017-08-22 15:37:59 +03:00
7fa8498b3a
adrv9371x: DAC_FIFO should get the dma_rst from sys_dma_rstgen
2017-08-22 09:16:21 +01:00
b0b79013f7
fmcomms11: Connect data underflow to the core
2017-08-22 09:16:21 +01:00
d5eedf8356
daq2: Add support for Arria10 SoC platform
...
Add support for the AD-FMCDAQ2-EBZ on the Arria10 SoC development board platform.
In its default configuration the Arria10 SoC development board is not fully
compatible with the AD-FMCDAQ2-EBZ and a slight rework is necessary,
changing the position of four 0 Ohm resistors:
R610: DNI -> R0
R611: DNI -> R0
R612: R0 -> DNI
R613: R0 -> DNI
R620: DNI -> R0
R632: DNI -> R0
R621: R0 -> DNI
R633: R0 -> DNI
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:21:42 +02:00
17d3e3c64b
daq2: daq2_qsys.tcl: Convert to ADI JESD204
...
Convert the DAQ2 project for Intel/Altera platforms to the ADI JESD204
framework.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:21:42 +02:00
Adrian Costina
Istvan Csomortani
Michael Hennerich
Matt Fornero
AndreiGrozav
STEVE KRAVATSKY
Rejeesh Kutty
Lars-Peter Clausen