Commit Graph

9 Commits (2b84fbb3b321767071d0727db10bd2b51baadcfb)

Author SHA1 Message Date
Adrian Costina f2240633b2 axi_dac_interpolate: Add correction at the begining of the interpolation chain
The CIC filter introduces different amplifications depending on the
interpolation ratio. By adding a multiplier in the interpolation chain
the amplification can be compensated
2017-08-03 17:21:37 +03:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Lars-Peter Clausen 53c8ece8f8 axi_dac_interpolate: Reduce AXI address width
The axi_dac_interpolate does not use the full width of the AXI interface
address. It only responds to register access in the first 32 registers.

Reduce the size of the AXI address to 7 bit accordingly. This allows the
scripts to correctly infer the internal register map size which will cause
the interconnect to filter out access to these unused register.

This slightly reduces utilization by getting rid of some pipeline
registers.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:41 +02:00
Lars-Peter Clausen 834fcb7e27 axi_dac_interpolate: Reduce filter_mask signal width
Only the lower 3 bits of the filter_mask signal are used, no need to keep
the other bits around.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen 9c2c50728c axi_dac_interpolate: Move processing pipeline to own sub-module
Move the processing pipeline of the axi_adc_decimate core to its own
sub-module. This makes it easier to simulate the processing independent of
the register map.

Also since the filter is two instances of the same logic, one for each
channel, let the new sub-module model one channel and instantiate it twice.
This allows to change the implementation without having to change the same
code twice.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Adrian Costina be6fa287fa axi_dac_interpolate: Make dac_reset external 2017-04-18 12:17:39 +02:00
Adrian Costina 9c975211da axi_dac_interpolate: Initial commit 2017-01-31 16:22:49 +02:00