01aea161fa
Create CDC helper library
...
Move the CDC helper modules to a dedicated helper modules. This makes it
possible to reference them without having to use file paths that go outside
of the referencing project's directory.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
eb7171e212
daq3/kcu105- reorder refclk constraints
2017-05-19 11:41:45 -04:00
9055774795
all: Update license for all hdl source files
...
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.
New license looks as follows:
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.
Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
(at the option of the user):
1. The GNU General Public License version 2 as published by the
Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
OR
2. An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
ebeebdddf0
altera- infer latest versions
2017-05-12 13:40:14 -04:00
4eaa43f8e1
daq3: Update IP instantiations
2017-04-21 15:07:41 +03:00
942d69a30c
Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU
2017-04-18 10:57:16 +03:00
1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
8063ba2b66
make updates
2017-03-20 16:05:18 -04:00
d08d1d5a1b
adrv9371x ,daq3, fmcomms7, fmcomms11: add dac_fifo missing reset connection
2017-03-10 14:20:42 +02:00
0e002f2f31
daq3_a10gx: Set XCVR Tx/RX clk/data voltage levels at 1V
2017-03-09 08:50:55 +02:00
fb4a583613
projects/system_bd- adc/dac fifo board designs
2017-02-27 16:06:39 -05:00
6b1a8852a9
dacfifo- bypass port name change
2017-02-27 16:06:39 -05:00
c598e84258
remove processing order (no clock def dependency)
2017-02-22 16:02:08 -05:00
edd5e9570f
file renamed; sed output; fingers crossed
2017-02-22 15:56:37 -05:00
7c363cd5a7
daq3/a10gx/system_constr.sdc- fix typo
2017-02-03 09:26:07 -05:00
97d72d2f65
a10gx- xilinx/altera sync-up
2017-01-30 10:01:28 -05:00
b14e7fe4ee
daq3/kcu105- 1.25GSPS
2017-01-30 10:01:28 -05:00
661413627f
daq3- round about way to avoid ip getting locked
2017-01-20 15:55:33 -05:00
4a783d523d
projects/altera* - default & common qsys commands
2016-12-20 16:27:44 -05:00
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
801da3cb25
daq3/kcu105- fix timing violations
2016-12-06 12:31:40 -05:00
ad96c5e881
daq3/zc706: Change the speed grade of the FPGA to 3
2016-12-06 15:24:23 +02:00
170c781d02
hdlmake.pl- updates
2016-12-01 13:52:11 -05:00
862bd7ef2c
daq3/zc706- xcvr changes
2016-11-23 15:02:20 -05:00
cb97bc500a
hdlmake updates
2016-10-17 16:29:57 -04:00
905e29eb01
hdlmake- altera
2016-10-10 12:55:55 -04:00
fcd56a2f90
daq3/a10gx: Update project to the new GT framework
...
- Update common script
- Update system_top, some port names were changed
- Update constraint files
2016-10-10 16:22:08 +03:00
8965bcffb7
make: Update make files for DAQ3
2016-10-06 10:27:00 +03:00
9ace02a227
daq3/a10gx: Update project to the new GT framework
2016-10-06 10:25:25 +03:00
58c4abd8af
daq3/kcu105: Update project to the new GT framework
2016-10-06 10:23:52 +03:00
bab9b2df0b
daq3/zc706: Update project with the new transceiver modules
2016-10-05 17:41:25 +03:00
16ee1336c3
Makefile: Update make files
2016-09-15 11:41:06 +03:00
bae63ae5b1
version_upgrade: Update the DAQ3 project to 2016.2
2016-09-06 11:41:37 +03:00
ce1fed1ce6
dmafifo- adc/dac split
2016-08-16 12:54:39 -04:00
0b0aa8e6c0
Makefile: Add MMU option to altera makefiles
2016-08-11 17:46:54 +03:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
e42b4ea378
hdlmake- updates
2016-08-04 13:28:25 -04:00
999eccc134
daq3: Update A10GX project to Quartus 16.0
2016-08-01 16:19:43 +03:00
7ca8e10004
make: Update Make files
2016-08-01 14:24:48 +03:00
92c580a84d
daq3: A10GX, updated project to the TCL flow
2016-07-08 12:00:37 +03:00
eaf4d4a19d
makefile updates
2016-06-10 14:26:14 -04:00
d2fc64d130
daq3/a10gx: updates
2016-05-27 08:37:47 -04:00
9c6e80fca2
daq3/a10gx- qsys modifications
2016-05-24 03:15:45 -04:00
b0538a03a2
Make: Update
2016-05-06 16:44:24 +03:00
4863a04132
axi_adc/dacfifo: Split the intergration script file
...
Split the integration script file into two separate script files. Rename the
integration processes names to be more meaningful.
2016-05-05 09:53:55 +03:00
385ed31a45
make files update
2016-04-29 10:17:35 -04:00
679d471d75
Merge branch 'hdl_2016_r1' into dev
...
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
3006c5a223
make updates
2016-04-11 16:14:59 -04:00
21208ca208
Makefiles: Update Makefiles
2016-03-31 12:37:47 +03:00
d355aa0ea6
daq3/zc706: Updated design to 2015.4
2016-03-17 11:46:48 +02:00
012b095006
daq3: Updated common design to 2015.4
2016-03-17 11:44:27 +02:00
977d9d0624
Merge branch 'hdl_2015_r2' into dev
...
Conflicts:
projects/daq1/common/daq1_spi.v
2016-03-02 13:52:15 +02:00
40fb68dfd5
ad9265, ad9434, ad9467, daq1, daq2, daq3, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1, fmcomms6, fmcomms7, usdrx1: updated common spi module so that spi streaming is possible
2016-03-02 13:39:37 +02:00
f7e490c2b3
hdlmake.pl updates
2016-02-26 13:46:11 -05:00
83fd4a53a7
daq3/kcu105: updates
2015-12-14 09:29:48 -05:00
07316a905e
daq3/a10gx: sysref is lvds
2015-12-14 09:29:10 -05:00
6a9d1c431a
daq3/a10gx: updated to a10gx/quartus
2015-12-11 12:49:25 -05:00
dc84a9ad82
daq3/a10gx: updates
2015-12-10 16:06:14 -05:00
d944198212
daq3/a10gx: board updates
2015-12-10 09:45:20 -05:00
1a38ea205d
daq3/a10gx: copy
2015-12-10 09:42:56 -05:00
614babc18e
daq3/kcu105: copy
2015-12-10 09:41:47 -05:00
b0fef1122e
daq3/a10gx: copy
2015-12-10 09:41:37 -05:00
159f6c1216
Makefiles: Updated Makefiles
...
- for altera projects, taken into consideration of the new location for common qsys files
- for fmcomms5, added wfifo dependency
- for daq3, added mfifo dependency
2015-11-27 12:39:42 +02:00
a6f44949d6
daq3: updates
2015-11-13 13:17:11 -05:00
9d2b8809df
Makefiles: Updated Makefiles
2015-10-23 10:44:27 +03:00
b93af3c21e
daq3- bd updates
2015-09-30 10:11:49 -04:00
6c7316fbd0
daq3: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:56 +02:00
d52308f074
axi_dmac: Change parameter name 2D_TRANSFER
...
Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 10:14:22 +03:00
57cfb7cfb1
hdl/library: Update the IP parameters
...
The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
a7da779b94
Makefile: Updated Makefiles
2015-07-16 18:19:42 +03:00
6c0ad6ede8
daq3: bsplit/ccat -- removed
2015-07-15 13:05:53 -04:00
6862655b0d
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
71b5004b25
projects- drp moved to up-clock domain
2015-06-01 14:57:59 -04:00
a6cae6b477
iobuf: do is a system verilog keyword
2015-05-21 14:06:17 -04:00
6b9906b22b
Refresh Makefiles
...
Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 14:21:54 +02:00
c19749361d
Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
...
Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
00335a2af2
Makefile: Fix ZC706 Makefiles with propper address for the mig file
2015-05-11 10:25:07 +03:00
91279253ef
Makefiles: Added mig project file as a dependency for Microblaze based projects. Also updated usdrx1 a5gt Makefile
2015-05-08 15:31:40 +03:00
949abcdc8f
Makefile: Updated makefiles so that the project recipe does not depend on lib
2015-05-06 14:58:29 +03:00
dc2b37bd0c
Makefile: Added top level Makefile. Modified behavior of clean and clean-all
...
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.
The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
780455d68c
Makefile: Updated makefiles. Added makefiles for altera
2015-04-09 17:57:06 +03:00
5f8e9a74ea
makefile: updated
2015-04-07 16:32:01 -04:00
6d0a2bf64c
axi_adcfifo: added
2015-04-07 16:21:39 -04:00
f79a152958
Makefiles: updated all makefiles adding clean functionality
2015-04-03 11:57:54 +03:00
12e9ab7bdd
makefile: added
2015-04-01 16:29:05 -04:00
4e3e26a8dd
makefile: added
2015-04-01 16:29:03 -04:00
275ce42bc9
daq3: 2014.4 updates
2015-03-19 12:45:55 -04:00
caa0e27bd6
daq3: 2014.4 updates
2015-03-19 12:45:54 -04:00
423b436601
daq3: 2014.4 updates
2015-03-19 12:45:52 -04:00
0c94ea8d2b
daq3: 2014.4 updates
2015-03-19 12:45:51 -04:00
2fa475cca2
daq3: 2014.4 updates
2015-03-19 12:45:50 -04:00
e81327b794
daq3_zc706: Add constraint file for PLDDR
2014-12-18 10:08:33 +02:00
8121d11993
daq3_zc706: Connect PLDDR rst to external push button
2014-12-18 10:07:52 +02:00
090aed508e
daq3_zc706: Delete trailing spaces from system_top
2014-12-18 10:06:29 +02:00
1b4a4bc06e
daq3: compilation fixes - latest changes
2014-12-08 14:51:52 -05:00
c0d588ba8c
daq3: compilation fixes - latest changes
2014-12-08 14:51:52 -05:00
26d72d306e
daq3: compilation fixes - latest changes
2014-12-08 14:51:51 -05:00
cc265b6b9c
daq2/daq3/ad9625_fmc: Connect ADC DMA xfer_req signal
...
For proper operation the xfer_req signal needs to be connected from the ADC DMA to the DDR FIFO.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-29 18:15:54 +01:00
Lars-Peter Clausen
Rejeesh Kutty
Istvan Csomortani
Adrian Costina
AndreiGrozav