Commit Graph

1815 Commits (2ca2bf93831dcc57965e27310844ca005da46a13)

Author SHA1 Message Date
Adrian Costina 29ca9e4b8c vc707: common, fixed address range for flash 2015-05-23 00:14:08 +03:00
Adrian Costina 8bd5fa5802 kc705: Common, fixed address range for the flash. Changed the start address so that it won't interfere with other cores 2015-05-23 00:10:06 +03:00
Istvan Csomortani 660c84e01c axi_ad9434 : Update the IO delay interface 2015-05-22 19:47:09 +03:00
Istvan Csomortani f91fbf1bc1 ad9434_zc706: Fix SPI interface 2015-05-22 12:31:48 +03:00
Rejeesh Kutty a6cae6b477 iobuf: do is a system verilog keyword 2015-05-21 14:06:17 -04:00
Rejeesh Kutty ad3198f623 a10gx: top level fixes 2015-05-21 14:06:15 -04:00
Rejeesh Kutty 0c6ef203c0 iobuf: do is a system-verilog keyword 2015-05-21 14:06:13 -04:00
Rejeesh Kutty dc2eeebf2f upack: gen-name 2015-05-21 14:06:12 -04:00
Rejeesh Kutty 5c6340e927 dmac: clock-typo 2015-05-21 14:06:11 -04:00
Rejeesh Kutty e05ff26406 ad9144: ddata-typo 2015-05-21 14:06:09 -04:00
Rejeesh Kutty 8d78217f7b ad9680: missing prot. ports 2015-05-21 14:06:08 -04:00
Rejeesh Kutty 4c6a3afc88 ad9144: missing prot. ports 2015-05-21 14:06:06 -04:00
Lars-Peter Clausen a059290cf5 Remove axi_ad7175
This core has been superseded by the SPI Engine framework in combination
with the axi_generic_adc core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen c9832d2f84 Remove ad7175_zed project
This project has been superseded by the cn0363 project and can be removed.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen c53f8c15ee Add CN0363 project
Add support for the CN0363 (colorimeter) board connected to the ZED board.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen d43ba44d0f Add util_sigma_delta_spi peripheral
The util_sigma_delta_spi peripheral can be used to seperate the interleaved
SPI bus and DRDY signals for a ADC from the Analog Devices SigmaDelta
family.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen e6b58e8a20 Add SPI Engine framework
SPI Engine is a highly flexible and powerful SPI controller framework. It
consist out of multiple sub-modules which communicate over well defined
interfaces. This allows a high degree of flexibility and re-usability while
at the same time staying highly customizable and easily extensible.

Currently included are four components:
	* SPI Engine execution module: The excution module is responsible for
	  handling the low-level physical interface SPI logic.
	* SPI Engine AXI interface module: The AXI interface module allows
	  memory mapped acccess to a SPI bus control stream and can be used to
	  implement a software driver that controls the SPI bus.
	* SPI Engine offload module: The offload module allows to store a
	  predefined SPI Engine command and data stream which will be send out
	  when a external trigger signal is asserted.
	* SPI Engine interconnect module: The interconnect module allows to
	  combine multiple control streams into a single stream giving multiple
	  control modules access to a execution module.

For more information see: http://wiki.analog.com/resources/fpga/peripherals/spi_engine

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen a5b452cc27 Add axi_generic_adc core
The axi_generic_adc core is a simple core that doesn't do much more then
implementing the AXI ADC register map and routing the enable and overflow
signals to the farbic.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen 033713ccb5 Add cordic demodulator module
The cordic_demod module takes in phase and data on s_axis interface then
performs a cordic demodulation and outputs the resulting I and Q component
data on the m_axis interface.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen cefbe3a0ff scripts/adi_ip.tcl: Add option to specify reset interface direction
Allow to specify the direction of the reset signal for a interface, this is
useful if the core itself generates the reset signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen 6b9906b22b Refresh Makefiles
Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 14:21:54 +02:00
Adrian Costina ebbc0c6ed5 fmcomms5: zc706, removed debug related ila, as the pins were removed from the AD9361 IP 2015-05-21 14:19:22 +03:00
Adrian Costina 5ac7ebb8a3 axi_mc_*: Removed delay pins from up_adc_common 2015-05-21 14:03:58 +03:00
Istvan Csomortani a047d3990a fmcadc2_vc707: Fix interrupts
+ Remove some trailing whitespaces
+ Fix interrupt connections
2015-05-21 11:03:16 +03:00
Rejeesh Kutty 19b094cab5 daq2/a10gx- added jesd align 2015-05-20 15:39:27 -04:00
Rejeesh Kutty 465f7dff88 library/util_jesd_align -added 2015-05-20 15:38:43 -04:00
Rejeesh Kutty 9762c65868 library- jesd-align port name change 2015-05-20 14:25:21 -04:00
Rejeesh Kutty f1c30ac225 daq2/a10gx- qsys updates 2015-05-20 14:24:49 -04:00
Rejeesh Kutty 4927ca85c2 projects- jesd-align port name change 2015-05-20 14:24:26 -04:00
Rejeesh Kutty da0409b5a6 library- qsys components 2015-05-20 11:51:50 -04:00
Rejeesh Kutty 9b425736ac library: altera ip modifications 2015-05-20 10:41:21 -04:00
Rejeesh Kutty d48d3f4aa3 scripts/ip-alt- added 2015-05-20 09:11:18 -04:00
Rejeesh Kutty 52b6077a46 a10gx- 15.0 updates 2015-05-19 15:12:23 -04:00
Rejeesh Kutty e918588a4b library: remove axi-min-size parameter 2015-05-19 13:07:48 -04:00
Rejeesh Kutty 4fb1be0672 ad9680: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty af7afd7366 ad9671: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty 09a05fe9d8 ad9652: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty 13156593f8 ad9643: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty c8d3c04a05 ad9625: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty f53204f9f9 ad9467: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty 0805da3b6b fmcomms2/rfsom- enable dac delay 2015-05-18 16:45:54 -04:00
Rejeesh Kutty fe0ceb2530 delay-cntrl updates 2015-05-18 15:23:10 -04:00
Rejeesh Kutty 304a202d67 delay-cntrl updates 2015-05-18 14:57:05 -04:00
Rejeesh Kutty 2e257db109 delay-cntrl updates 2015-05-18 14:53:24 -04:00
Rejeesh Kutty 3e51d29f75 enable/txnrx- tdd changes 2015-05-18 14:28:20 -04:00
Rejeesh Kutty 0877c252ad delay-cntrl changes 2015-05-18 14:28:20 -04:00
Rejeesh Kutty 2bad47cf4f delay-cntrl: up-clk, direct access + tx 2015-05-18 14:28:20 -04:00
Rejeesh Kutty 6e047f78c6 delay-cntrl: up-clk, direct access + tx 2015-05-18 14:28:20 -04:00
Adrian Costina 2c1719095d util_axis_resize: Changed _ip.tcl format to the standard format 2015-05-18 17:25:07 +03:00
Adrian Costina c19749361d Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00