Commit Graph

22 Commits (2da7dd40796a132783e00d3bdcced1536d055e87)

Author SHA1 Message Date
AndreiGrozav 7194d2eccc axi_ad9361: Grup interfaces to add support for more carriers 2016-10-11 17:58:49 +03:00
Istvan Csomortani aad8c265bc lib_refactoring: Fix path for CMOS sources 2016-08-08 15:07:54 +03:00
Istvan Csomortani df36902713 lib_refactoring: Fix path of the IO macros 2016-08-08 15:07:19 +03:00
Rejeesh Kutty f411d29e30 ad9361- a10soc changes 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 583ef82fd0 ad9361- cmos mode 2016-03-04 10:39:48 -05:00
Istvan Csomortani fc0f4bc414 axi_ad9361: Delete the old sync generator from the core
+ Define two control signal for util_tdd_sync : tdd_sync_en and tdd_terminal_type
+ Delete to old ad_tdd_sync.v instances from the core
+ Update Make files
+ Update ad_tdd_control: add additional CDC logic for tdd_sync (the sync comes from another clock domain)
+ Update the ad_tdd_sync module: it's just a simple pulse generator, the pulse period is defined using a parameter, pulse width is fixed: 128 x clock cycle
+ Update TDD regmap: tdd sync period is no longer software defined
2015-11-11 11:06:19 +02:00
Rejeesh Kutty 664ef017bb ad9361- ensm through dev-if 2015-08-27 11:41:52 -04:00
Rejeesh Kutty b0d22d323a ad9361- axi-clock definitions 2015-08-26 14:11:43 -04:00
Rejeesh Kutty 7780b3a3a2 2015.2 updates 2015-08-26 11:33:27 -04:00
Istvan Csomortani 7b858bc5ad Revert commit 6b99ce
Revert 6b99ce2482
2015-08-26 13:48:28 +03:00
Adrian Costina 6b99ce2482 library: Added common constraints for all cores. Commented code that needs to be updated to 2015.2 2015-08-20 18:17:38 +03:00
Istvan Csomortani d2c99acae8 fmcomms2/TDD: Update synchronization interface
Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 15:14:36 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Rejeesh Kutty 6338dfd8b7 ad9361: ip defaults & rst output 2015-06-05 09:19:39 -04:00
Rejeesh Kutty 91b0f70972 library: remove drp cntrl 2015-06-02 09:58:57 -04:00
Istvan Csomortani 7c9bc40c75 axi_ad9361&TDD: Update TDD
+ Delete unnecessary registers
+ Add the module ad_addsub.v to resolve additions and subtractions inside TDD control
+ Redefine the burst logic
+ Redesign the control signal generations
+ Note: This patch fix the TDD related timing violations
2015-05-13 14:03:01 +03:00
Istvan Csomortani 2e7135c3c2 axi_ad9361_tdd: Initial commit.
Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 12:20:44 +03:00
Lars-Peter Clausen e3b834ea02 axi_ad9361: Add CDC constraints
Add proper constraints for all the CDC synchronizer paths to the axi_ad9361
core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 20:12:06 +02:00
Rejeesh Kutty a388ccab0a fmcomms2/c5soc: initial checkin 2014-07-02 14:56:00 -04:00
Rejeesh Kutty e650253013 library: register map changes and for mathworks 2014-06-24 14:22:05 -04:00
Rejeesh Kutty 842cd98b61 ad9361: adc loopback option 2014-05-27 12:15:02 -04:00
Rejeesh Kutty 580808e146 axi_ad9361: added 2014-03-11 20:01:55 -04:00