Commit Graph

198 Commits (2dd6bb0cb82e782eeb9b783de626b552d10d101c)

Author SHA1 Message Date
Istvan Csomortani 2dd6bb0cb8 up_drp_cntrl: Delete unused module 2016-07-20 14:17:04 +03:00
Istvan Csomortani af9915b060 up_axis_dma_*: Delete unused modules 2016-07-20 14:17:04 +03:00
Istvan Csomortani df43ca9332 ad_axis_dma_*: Delete unused modules 2016-07-20 14:17:04 +03:00
Istvan Csomortani 64633e519c Merge remote-tracking branch 'origin/dev_ad7616' into dev 2016-06-29 12:32:39 +03:00
AndreiGrozav aee38e1cc9 up_hdmi_tx: Fixed data path width 2016-06-14 14:27:03 +03:00
Istvan Csomortani 9d1ae436b1 common/util_pulse_gen: Rename the ad_tdd_sync module 2016-06-09 10:07:47 +03:00
AndreiGrozav f10c1e6e93 axi_hdmi_tx: Remove hdmi_full_range register 2016-05-27 14:04:40 +03:00
Rejeesh Kutty 6bc05fc844 ad_*_in: register post-iob 2016-05-16 12:19:38 -04:00
Rejeesh Kutty cd7c9c99ed ad_*_clk: altera-pll not supported by qsys flow 2016-05-16 12:19:38 -04:00
Rejeesh Kutty 9cd6e2da51 quartus-mess- altddio direct instantiation 2016-05-09 13:54:08 -04:00
AndreiGrozav 726ddb6e93 ad_lvds_clk: Fixed assignment mismatched 2016-05-09 10:32:18 +03:00
AndreiGrozav b36c722ec9 up_hdmi_tx: Discard the standard default values
Restore the base functionality of the core. Changing the data format
will not set by default its standard maximum and minimum data clipping
ranges.
2016-05-05 13:41:46 +03:00
Rejeesh Kutty d82ca5dc3c library/common- altera variations 2016-05-04 13:42:11 -04:00
Rejeesh Kutty 89f5d2394e altera- clock variations 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 3563c2212c common/altera- removed dcfilt/mul 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 0260280db1 common/altera- data path 2016-04-29 10:17:35 -04:00
Rejeesh Kutty ed62101308 common/altera: primitives 2016-04-29 10:17:35 -04:00
Istvan Csomortani ad227c1af0 up_axi: Wait more to a valid read acknowledge. 2016-04-25 10:34:17 +03:00
AndreiGrozav 679d471d75 Merge branch 'hdl_2016_r1' into dev
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
Istvan Csomortani 42cd05ab19 ad_mem_asym: Add support for more ratios.
Supported ratios: 1:1/1:2/1:4/1:8/2:1/4:1/8:1
2016-04-19 11:18:30 +03:00
AndreiGrozav 6fe41ebb08 axi_hdmi_tx: Upgrade hdmi clipping process
-added two registers that control the clipping ranges (0x01a and 0x01b)
-extend clipping process for all output data formats
2016-04-12 22:01:07 +03:00
Rejeesh Kutty 65b2e51958 common/mmcm: add another clock 2016-03-22 12:50:59 -04:00
Rejeesh Kutty 7a320a3d34 ad_lvds* - updates 2016-03-04 10:39:48 -05:00
Rejeesh Kutty 7d2939be92 ad9361- cmos mode initial commit 2016-03-04 10:39:48 -05:00
Rejeesh Kutty a8e9d72273 adc/dac - prefix parameters 2016-02-17 14:16:04 -05:00
Istvan Csomortani e381d5170c util_tdd_sync: Update the synchronization interface
Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-12 14:27:37 +02:00
Istvan Csomortani d1e638349b ad_serdes_clk : The reference clock selection line should by tied to 1
Just the CLKIN1 is used in the MMCM.
2016-01-19 11:18:00 +02:00
Istvan Csomortani 29a0f27cd1 ad_edge_detect: Add a flop to output, reset is active high 2015-12-14 15:40:29 +02:00
Istvan Csomortani 12c95b059d ad_tdd_control: Remove tdd_enable_synced control line
For a better timing and control, the valid control lines are gated with flops, instead of combinatorial logic.
This is the main reason why we do not need the tdd_enable_synced signal anymore. The out coming data is delayed by one clock cycle to keep data and control lines synced.
2015-12-03 11:16:28 +02:00
Adrian Costina 5cf45b2978 axi_clkgen: Added phase related parameters 2015-12-02 18:50:23 +02:00
Adrian Costina 667e49fe41 library: Axi_clkgen, added register for controlling the source clock.
Address is 0x11 /0x44.
With the default value, 0, clock 1 is selected. If set to 1, clock 2 is selected
2015-11-25 11:16:32 +02:00
Istvan Csomortani 593c486168 ad_tdd_control: The state machine goes from OFF to ON, when a valid sync is received 2015-11-24 15:15:53 +02:00
Istvan Csomortani c70be7391f ad_tdd_control: Avoid unnecessary reset on control lines
No need to reset for tdd_last_burst, it's value depends on the tdd_burst_counter.
2015-11-24 15:13:18 +02:00
Adrian Costina 985f2ca020 library: ad_rst, added comment so that the registers are not minimized away 2015-11-24 10:33:38 +02:00
Istvan Csomortani 9ba8c059ce ad_tdd_sync: Fix reset value of the pulse_counter 2015-11-13 18:31:24 +02:00
Istvan Csomortani d6eae81bc1 axi_ad7616: Add the control module to the core, finish up SPI integration 2015-11-13 18:14:21 +02:00
Adrian Costina 3c27b3a4c5 ad_lvds_in: Add single ended option 2015-11-13 12:13:09 +02:00
Istvan Csomortani b17fec689e ad_tdd_control: An active sync pulse can NOT be a reset for the control lines
By reset the control lines (RF, VCO and DP) on an active sync pulse, can cause glitches on the ENABLE/TXNRX lines. The sync pulse resets just the TDD counter.
2015-11-11 11:13:33 +02:00
Istvan Csomortani fc0f4bc414 axi_ad9361: Delete the old sync generator from the core
+ Define two control signal for util_tdd_sync : tdd_sync_en and tdd_terminal_type
+ Delete to old ad_tdd_sync.v instances from the core
+ Update Make files
+ Update ad_tdd_control: add additional CDC logic for tdd_sync (the sync comes from another clock domain)
+ Update the ad_tdd_sync module: it's just a simple pulse generator, the pulse period is defined using a parameter, pulse width is fixed: 128 x clock cycle
+ Update TDD regmap: tdd sync period is no longer software defined
2015-11-11 11:06:19 +02:00
Adrian Costina e7fd964874 axi_clkgen: Added a second input clock option 2015-11-06 17:55:29 +02:00
Adrian Costina 6cfc13a9dd common: Allow for the memory to be also symetrical 2015-11-04 13:28:02 +02:00
Rejeesh Kutty f1ed27105f library/common- reset fix 2015-10-23 14:32:35 -04:00
Istvan Csomortani 8ecdb4a4ca library/tdd_control: Add common registers to the register map and fix init value of a register
+ Software in general needs to have access to the VERSION register.
+ tdd_sync_d3 registers init value should be 1'b0
2015-10-16 11:57:54 +03:00
Adrian Costina 96d363849e ad_dds: Registered dds_scale so that Vivado can optimally map the dsp block 2015-10-09 13:43:14 +03:00
Rejeesh Kutty 5c3f90a676 up_gt: separate pll resets to tx/rx 2015-10-02 13:58:30 -04:00
Istvan Csomortani 97a9ecfc9a axi_hdmi_rx: Update constraint file and fix reset line 2015-09-29 18:49:30 +03:00
Istvan Csomortani b765be568f up_gt_channel: Delete the register, which stores transceiver type
Transceiver type is stored in axi_jesd_gt/up_gt only.
2015-09-29 14:23:42 +03:00
Istvan Csomortani cffb2e6226 up_gt_channel: Move the VERSION register to up_gt_channel, in order to preserve its address 2015-09-29 14:19:52 +03:00
Istvan Csomortani a0ac0e912b up/ad_gt_common/channel: Cosmetic changes 2015-09-29 14:16:24 +03:00
Istvan Csomortani c03983ca54 ad_tdd_sync/control: Update TDD logic
+ Redesign the TDD counter FSM
+ Make the sync logic independent from the tdd control
2015-09-25 19:11:23 +03:00