2e17e67627
common/a5gt- altera 16.1 updates
2017-06-09 16:20:15 -04:00
ebeebdddf0
altera- infer latest versions
2017-05-12 13:40:14 -04:00
cb3d1883bc
fmcjesdadc1/a5gt- hard placement of ddr hr/qr registers
2017-02-17 15:21:33 -05:00
18660c7ab4
fmcjesdadc1/a5gt: ddr3 use ip constraints
2016-12-22 14:14:21 -05:00
1ceec2e2a9
projects/a5gt- use 50m afi clock for cpu- xcvr reconfig timing
2016-12-22 14:14:21 -05:00
959055bd54
common/a5gt- updates
2016-11-10 16:56:35 -05:00
c6730ab2d7
fmcjesdadc1/a5gt- updates
2016-11-10 11:36:41 -05:00
8af0731bb0
a5gt- qsys2tcl flow
2016-11-10 11:30:18 -05:00
0f37dd6424
fmcjesdadc1: Fixed project
...
- changed system_project.tcl so that all base designs to be included
- changed DMA properties to take into consideration the new parameter names
- changed reset bridges to asynchronous
- increased maximum burst size of the DMA bridge
- changed the data_width of the memory bus to 256, as with 512 timing violations may occur
- changed base addresses for the base system to be the same as in the previous release
2016-02-19 14:09:57 +02:00
31ab81d627
a5gt: Updated ethernet clock constraints
2015-07-27 16:02:51 +03:00
a1733238df
fmcjesdadc1- base/board split up
2015-07-23 15:21:53 -04:00
3e2712cf18
a5gt-base: initial updates
2015-07-22 15:22:22 -04:00
64070b6f27
a5gt- base system
2015-07-22 15:04:59 -04:00
15740a7d34
fmcjesdadc1- 15.0 updates
2015-06-24 05:31:09 -04:00
a8a71b4971
alt-tq: common file
2015-06-04 11:00:25 -04:00
5a77ab0161
a5gt:common: Added phy reset signal from ethernet in pin assignments
2015-01-23 12:31:41 +02:00
3deb55bb98
a5gt: ethernet i/o changed to lvds
2014-09-04 11:19:24 -04:00
cb29b83b05
a5gt: updates to match a5gt
2014-08-25 10:46:59 -04:00
04ab34c8ed
a5gt: ethernet assignments
2014-04-03 20:50:16 -04:00
0d678b89ed
altera a5gt fmcjesdadc1 setup
2014-04-01 11:46:37 -04:00
Rejeesh Kutty
Adrian Costina