Commit Graph

5 Commits (2f35ce8a5126ef2a358f7b07087b48160bb9f278)

Author SHA1 Message Date
Iulia Moldovan 0c0617d49e libraries: Update modules according to guideline
* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Lars-Peter Clausen 764f31463e axi_dmac: tb: Allow testing asymmetric interface widths
One of the major features of the DMAC is being able to handle non matching
interface widths for the destination and source side.

Currently the test benches only support the case where the width for the
source and the destination side are the same. Extend them so that it is
possible to also test and verify setups where the width is not the same.

To accomplish this each byte memory location is treated as if it contained
the lower 8 bytes of its address. And then the written/read data is
compared to the expected data based on that.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-30 23:41:49 +02:00
Lars-Peter Clausen d72fac4b1e Add missing timescale annotations
For consistent simulation behavior it is recommended to annotate all source
files with a timescale. Add it to those where it is currently missing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-17 10:32:47 +03:00
Laszlo Nagy 3f94fec620 axi_dmac/dma_write_tb: added data integrity check
Added passing condition checking.
Added variable request sizes
2018-05-03 14:49:06 +02:00
Lars-Peter Clausen 24d17e8bcc axi_dmac: Add transfer testbenches
Add simple transfer testbenches that test the read and write to AXI memory
paths of the DMAC.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-03 14:49:06 +02:00