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897 Commits (30a869b02a6f144929280ba3f7d321c496eb0c3d)

Author SHA1 Message Date
Istvan Csomortani 2912372d6e ad9625_fmc: Add support for AD-JESDCLOCK1-EBZ 
Connect the SPARE_CLOCK_DUT pin to GPIO, this will be used to reset the AD9527.
The SPI interface for the clock chip is already integrated into the design.
 2014-11-18 14:11:51 +02:00
Istvan Csomortani bbf1f0c156 adi_project: Add board definition for mitx045 2014-11-18 10:05:57 +02:00
Istvan Csomortani e3378cd6cb mitx045_board_definition: revert old board definition file 
Revert commit 4f6aa159b8. Those changes won't solve the issue.
mitx045.xml is the supported version under 2013.4
 2014-11-18 10:05:55 +02:00
Istvan Csomortani 6e194dbcc0 adv7511_ac701: Fix project source files definition 2014-11-18 10:05:54 +02:00
Istvan Csomortani 766589637e prcfg_zc706: Update data width and project script 2014-11-18 10:05:53 +02:00
Istvan Csomortani 42874bfe81 prcfg_library: Major update 
Get rid of the QPSK symbol wrapper for now. The DMA data path is using the 2 LSB bits.
 2014-11-18 10:05:52 +02:00
Istvan Csomortani 5c7e8eb926 prcfg_setup: Fix data width, delete invalid ILA configurations 2014-11-18 10:05:51 +02:00
Istvan Csomortani bd57c2246e prcfg: Increase the PR portion area in order to increase the DSP resource. 2014-11-18 10:05:49 +02:00
Istvan Csomortani 344f1bb539 adv7511_kc705: Fix project source definition 2014-11-18 10:05:48 +02:00
Adrian Costina 01b3495a81 fmcomms1: Updated ZC706 project to be compatible with util_wfifo and increased system_constr.xdc priority 2014-11-17 18:33:21 +02:00
Adrian Costina 20a3f322e7 fmcomms1: Updated zc702 project 
- fixed timing constraints, increased system_constr.xdc priority
- used ad_iobuf
- updated interrupt system to latest implementation
 2014-11-17 18:32:12 +02:00
Adrian Costina adcd16d033 fmcomms1: Updated zed project 
- fixed timing constraints
- used ad_iobuf
- updated interrupt system to latest implementation
 2014-11-17 18:31:24 +02:00
Rejeesh Kutty a4724f8396 es: added kcu105 gth 2014-11-17 09:55:12 -05:00
Rejeesh Kutty b1c91fac92 es: added kcu105 gth 2014-11-17 09:55:10 -05:00
Rejeesh Kutty fd305f2eff es: added kcu105 gth 2014-11-17 09:55:09 -05:00
Adrian Costina 6dd1226696 axi_ad9643: Fixed constraint file 2014-11-17 12:12:09 +02:00
Adrian Costina 8831d9dbd7 axi_ad9122: fixed constraint file 2014-11-17 12:11:20 +02:00
Adrian Costina 2744d0cb37 util_wfifo: Update to implement flip flops 2014-11-17 12:10:21 +02:00
Rejeesh Kutty 5d1a0a14bf ad9625x2_fmc: dma fifo changes 2014-11-14 16:00:32 -05:00
Rejeesh Kutty 41ffc66c26 fifo2s: removed m interface 2014-11-13 15:00:03 -05:00
Rejeesh Kutty 2eb80715e3 ad9625_fmc: dma fifo changes 2014-11-13 14:13:00 -05:00
Istvan Csomortani eaacd4d49a adi_project.tcl: Fix message severity (working solution) 
Need to define the default/initial severity too.
 2014-11-13 18:55:43 +02:00
Istvan Csomortani 4bcf338e9b adi_project.tcl : Fix message severity 
When message severity is set to 'error', need to do it quiet, other way the tool will stop after synthesis, complaining for previous errors.
 2014-11-13 16:33:47 +02:00
Istvan Csomortani 5baa015246 kc705_base: Delete timing constraints 2014-11-13 16:30:37 +02:00
Rejeesh Kutty 3915f7d5f4 daq2: kcu105 dma-fifo changes 2014-11-12 15:25:13 -05:00
Rejeesh Kutty d79e95b774 daq2: dma-fifo changes 2014-11-12 15:24:54 -05:00
Rejeesh Kutty 074662a622 dmafifo: common interface with fifo2s 2014-11-12 15:24:31 -05:00
Rejeesh Kutty 8761db438e axi_fifo2f: common interface with fifo2s 2014-11-12 15:15:32 -05:00
Rejeesh Kutty 855919ee8e plddr3: internal buswidth/clock conversion 2014-11-12 14:43:50 -05:00
Rejeesh Kutty dbf5acde76 plddr3: internal buswidth/clock conversion 2014-11-12 14:43:49 -05:00
Rejeesh Kutty c6af2696b3 plddr3: internal buswidth/clock conversion 2014-11-12 14:43:48 -05:00
Rejeesh Kutty 925e966eb6 axi_fifo2s: fifo full replaced with ready 2014-11-12 14:43:47 -05:00
Rejeesh Kutty 5fc4f1b000 axi_fifo2s: buswidth fix 2014-11-12 14:43:46 -05:00
Rejeesh Kutty d204a7c2b7 axi_fifo2s: include bus width/clock transfer 2014-11-12 14:43:44 -05:00
Rejeesh Kutty e7cec7171e axi_fifo2s: include bus width/clock transfer 2014-11-12 14:43:43 -05:00
Rejeesh Kutty 4381f20a6a axi_fifo2s: include bus width/clock transfer 2014-11-12 14:43:42 -05:00
Rejeesh Kutty 9f2dbad539 axi_fifo2s: include bus width/clock transfer 2014-11-12 14:43:41 -05:00
Rejeesh Kutty e683b5868e axi_fifo2s: include bus width/clock transfer 2014-11-12 14:43:40 -05:00
Rejeesh Kutty 81b4cd532d axi_fifo2s: include bus width/clock transfer 2014-11-12 14:43:38 -05:00
Rejeesh Kutty 888ab888d2 axi_fifo2s: include bus width/clock transfer 2014-11-12 14:43:37 -05:00
Istvan Csomortani f8e7796592 axi_jesd_gt: Fix lane number parameters 2014-11-12 17:43:32 +02:00
Istvan Csomortani bf62665c56 prcfg_qpsk: Add Simulink model 
Matlab version used: R2014a, HDL Coder 3.3
 2014-11-12 15:44:38 +02:00
Adrian Costina ce92d49565 adv7511: Updated VC707 project to include linear flash 2014-11-12 11:46:01 +02:00
Istvan Csomortani 897f5e219d ad9625_zc706: Update GT configuration 2014-11-11 19:25:30 +02:00
Istvan Csomortani 776a396141 adi_project.tcl: Add new message severity definition 
Set "Parameter does not exist!" message severity to error.
 2014-11-11 19:20:40 +02:00
Rejeesh Kutty 8147fa0eb6 fmcomms7: asymmetric no of lanes 2014-11-11 08:54:27 -05:00
Rejeesh Kutty 439cbecf7c fmcomms7: asymmetric no of lanes 2014-11-11 08:54:26 -05:00
Rejeesh Kutty b96a8d01c3 fmcomms7: asymmetric no of lanes 2014-11-11 08:54:25 -05:00
Rejeesh Kutty 64ec633438 gt: asymmetric no of lanes 2014-11-11 08:54:24 -05:00
Paul Cercueil 97fa063341 fmcadc3: Fix pre-processing of ADC data 
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
 2014-11-11 11:49:40 +01:00