318dcbb5d9
adrv9371x: Set up the defualt clock output control
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The TX side runs on QPLL, and the RX and RX_OS runs on CPLL by default.
The OUTCLK frequency is the same as the REFCLK.
The main reason of this modification is that the links should come up
without any DPR access, after power up, using the default reference clock
configuration (122.88 MHz).
2018-04-11 15:09:54 +03:00
8b671fa7ae
ad77681evb: Add upscaler to the data path
2018-04-11 15:09:54 +03:00
e782ed06cb
adaq7980: Expouse the ADC sampling rate in system_bd.tcl
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This way the user do not need to modify the block design, just
set the required rate in system_bd.tcl.
This commit does not contain any functional changes.
2018-04-11 15:09:54 +03:00
bfc8ec28c3
util_axis_fifo: instantiate block ram in async mode
...
In cases when a shallow FIFO is requested the synthesizer infers distributed RAM
instead of block RAMs. This can be an issue when the clocks of the FIFO are
asynchronous since a timing path is created though the LUTs which implement the
memory, resulting in timing failures. Ignoring timing through the path is not a
solution since would lead to metastability.
This does not happens with block RAMs.
The solution is to use the ad_mem (block RAM) in case of async clocks and letting
the synthesizer do it's job in case of sync clocks for optimal resource utilization.
2018-04-11 15:09:54 +03:00
51380fbea4
daq3/kcu105: Define transceiver type as Ultrascale
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When software configures the system it takes into account the transceiver type.
By default, the XCVR_TYPE is 0 for 7 Series.
2018-04-11 15:09:54 +03:00
8e042193be
DE10: Initial commit
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These modifications were taken from the old dev branch.
2018-04-11 15:09:54 +03:00
8c964389f6
sidekiqz2: Initial commit
2018-04-11 15:09:54 +03:00
9a44ab921b
adrv9371: Swap CSN lines to preserve consistency
2018-04-11 15:09:54 +03:00
3277ea4be0
ad_dcfilter: Enable output registers in DSP48E1
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Pipelining the DSP48 output will improve performance and often saves power so
it is suggested whenever possible to fully pipeline this function.
2018-04-11 15:09:54 +03:00
7824f79fc0
adrv9371x:zcu102: Use explicit PACKAGE_PIN definitions for JESD204 lanes and reference clocks
2018-04-11 15:09:54 +03:00
09a6eb5360
up_dac_common: Explicitly define boolean parameter as a 1 bit value
2018-04-11 15:09:54 +03:00
a1e2b60cb3
ad_xcvr_rx_if: rx_ip_sof_d register has a width of 4 bits
2018-04-11 15:09:54 +03:00
b6770effc5
avl_dacfifo: Add missing wire declaration
2018-04-11 15:09:54 +03:00
f100a6bf21
avl_dacfifo: Delete deprecated false path definition
2018-04-11 15:09:54 +03:00
425e803364
license: Fix a spelling mistake
2018-04-11 15:09:54 +03:00
34994222b4
license: Update old license headers
2018-04-11 15:09:54 +03:00
ee79ba5686
axi_hdmi_tx: removed unused registers
2018-04-11 15:09:54 +03:00
9a76bd4536
axi_adxcvr: Set the init value of the configuration registers
2018-04-11 15:09:54 +03:00
571b721274
util_adxcvr: CPLLPD should be used for reset
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For CPLL reset the CPLLPD ports should be used, instead of the
CPLLRESET. The recommended reset width is above 2us.
See UG576 pg. 60 for more detail.
2018-04-11 15:09:54 +03:00
4e60f15e7f
axi_clkgen: Add a parameter to control the clock source options
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Add a parameter to the control the clock source option of the MMCM. If
the MMCM has only one clock source the CLKSEL pin will be tied to VDD.
The previous version added a redundant path between the CLKSEL port and
register map.
2018-04-11 15:09:54 +03:00
bd8c71c2ec
adrv9371x:zcu102: Set DEVICE_TYPE to ultrascale
2018-04-11 15:09:54 +03:00
d1b91c6019
fmcadc2: Delete redundant settings
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This project has only receive paths, all transmit related setting of the
transceivers are redundant.
2018-04-11 15:09:54 +03:00
f565818ab2
adi_xilinx_msg: eth_avb is not used by our designs
2018-04-11 15:09:54 +03:00
72431ff952
a10soc: Connect AXI register reset
2018-04-11 15:09:54 +03:00
a5407702bb
util_adxcvr: Don't show reset ports for disabled lanes
2018-04-11 15:09:54 +03:00
0d01c08b00
util_[c|u]pack_dsf: clear syntehsis warnings
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Remove unused registers and move register definitions to the generate block
that is actually using it.
2018-04-11 15:09:54 +03:00
bce0cf8e22
util_[w|r]fifo: Reduce synthesis warnings
2018-04-11 15:09:54 +03:00
eedd8ed5d8
up_delay_cntrl: Fix synthesis warnings, no functional changes
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Reduce the number of synthesis warnings with the help of a generate
statement. When the block is disabled do not generate any logic.
2018-04-11 15:09:54 +03:00
b4ab639db5
up_[adc|dac]_common: Define the DPR registers only when the interface is enabled
2018-04-11 15:09:54 +03:00
5cba46165a
axi_dmac: fix synthesis warnings
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Separated the 2D transfer registers to a separate generate block
2018-04-11 15:09:54 +03:00
c0184bce59
adrv9379: Fix lane assignment, according to schematic
2018-04-11 15:09:54 +03:00
4bcf45a17a
common: clean up synthesis warnings
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Removed unused registers and define registers only when they are in use.
2018-04-11 15:09:54 +03:00
b6d2def504
axi_ad9361: clear synthesis warnings
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Defined the delay registers only when they are used.
2018-04-11 15:09:54 +03:00
6f52ddb2c7
adrv936x: Fix Ethernet
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Explicitly select MIO 52 and 53 pins to be part of MDIO port.
MIO_52_PIN (MDIO 0 Clock, Output)
MIO_53_PIN (MDIO 0 Data, Input/Output)
After the tool version change, this pins where by default connected
as MIO GPIOs.
2018-04-11 15:09:54 +03:00
5bfc585524
axi_dmac: Added MAX_BYTES_PER_BURST and DISABLE_DEBUG_REGISTERS parameters to Intel IP
2018-04-11 15:09:54 +03:00
25ffb91dc6
axi_hdmi_tx: Updated .sdc constraints
2018-04-11 15:09:54 +03:00
a0cb3af11d
axi_hdmi_tx: Use abstract multiplier module supporting both Xilinx and Intel FPGAs
2018-04-11 15:09:54 +03:00
9877862517
fmcomms2/zc702: Fix implementation timing issues
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Changed the tool strategies for synthesis and implementation.
2018-04-11 15:09:54 +03:00
1a9497b5b6
daq3: Add parameters for default xcvr configuration
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The default configuration should be:
- line rate 12.33 Gbps
- core clk 308 MHz
2018-04-11 15:09:54 +03:00
7f377454a8
daq2/fmcadc4/daq3: Disable the transfer start sync on the ADC DMA
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Explicitly disable the "Transfer Start Synchronisation Support"
since the sync lines are not connected in this project.
If the sync input line (s_axi_user[0] or fifo_wr_sync) are not connected,
Vivado 2017.4.1 no longer connects them to the defaultValue defined
in the axi_dmac ip (1). Instead he uses the defaulValue field defined
in the interface definition which in case of both interfaces is 0;
2018-04-11 15:09:54 +03:00
d13ff8df1e
axi_dmac: In SDP mode REGCEB is connected to GND
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In newer version of Vivado (e.g. 2017.4) the REGCEB pin of the block ram
macro is connected to ground. So the following false path became
redundant.
2018-04-11 15:09:54 +03:00
fcbc977cd8
axi_ad7616: Add missing port to instantiation
2018-04-11 15:09:54 +03:00
f605b428fc
spi_engine:axi_spi_engine: Add missing port to instantiations
2018-04-11 15:09:54 +03:00
7d0b162eda
axi_ad9963: Fix port dependency definition
2018-04-11 15:09:54 +03:00
aa90d9a6e1
ad738x_zed: Fix SCLK's pin assignment
2018-04-11 15:09:54 +03:00
11ece90435
ad738x: Add system variables for configuration
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- In system_bd define variable $adc_resolution, $adc_num_of_channels and
$adc_sampling_rate.
- Add support for 12 and 14 bit resolution
2018-04-11 15:09:54 +03:00
a7b98c397a
ad_tdd_control: Fix the tdd_burst_counter implementation
2018-04-11 15:09:54 +03:00
53fa482837
ad7134_fmc: Initial commit
2018-04-11 15:09:54 +03:00
cd94f2f249
util_axis_upscale: Initial commit
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This module upscale an n*sample_width data bus into a 16 or 32*n data
bus. The samples are right aligned and supports offset binary or two's
complement data format.
2018-04-11 15:09:54 +03:00
269ae40f66
spi_engine: Add support for 8 SDI lines
2018-04-11 15:09:54 +03:00
Istvan Csomortani
Laszlo Nagy
AndreiGrozav
Rejeesh Kutty
Adrian Costina