16 Commits (320f87d63bb7764b8a25147a82094e13e272efb5)

Author	SHA1	Message	Date
Istvan Csomortani	df36902713	lib_refactoring: Fix path of the IO macros	2016-08-08 15:07:19 +03:00
Rejeesh Kutty	d254fa841b	library- altera updates	2016-05-23 10:55:07 -04:00
Rejeesh Kutty	ff1d98a0c7	ad9144: duplicate include	2015-12-10 16:02:35 -05:00
Adrian Costina	f51871c1e4	axi_ad9144: Updated altera interfaces, added FIFO conduits per channel	2015-11-24 11:44:07 +02:00
Istvan Csomortani	57cfb7cfb1	hdl/library: Update the IP parameters ... The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N	2015-08-19 14:11:47 +03:00
Rejeesh Kutty	3101045109	qsys- library group	2015-07-17 10:07:15 -04:00
Rejeesh Kutty	60c344cea6	ad9144- qsys needs interface signal name matching	2015-07-15 15:59:51 -04:00
Rejeesh Kutty	c69e36314c	ad9144- remove avalon streaming	2015-07-13 10:03:16 -04:00
Rejeesh Kutty	e02273781f	ad_rst- non lpm version	2015-06-04 10:53:12 -04:00
Rejeesh Kutty	91b0f70972	library: remove drp cntrl	2015-06-02 09:58:57 -04:00
Rejeesh Kutty	d7b68c39ef	altera- sdc	2015-06-01 10:59:59 -04:00
Rejeesh Kutty	e05ff26406	ad9144: ddata-typo	2015-05-21 14:06:09 -04:00
Rejeesh Kutty	465f7dff88	library/util_jesd_align -added	2015-05-20 15:38:43 -04:00
Rejeesh Kutty	da0409b5a6	library- qsys components	2015-05-20 11:51:50 -04:00
Rejeesh Kutty	9b425736ac	library: altera ip modifications	2015-05-20 10:41:21 -04:00
Rejeesh Kutty	553f89f59d	ad9144- add hw tcl	2015-05-12 14:39:57 -04:00